Article

Low Power BIST Design by Hypergraph Partitioning: Methodology and Architectures

Authors:

S. PravossoudovitchAuthors Info & Claims

ITC '00: Proceedings of the 2000 IEEE International Test Conference

Page 652

Published: 03 October 2000 Publication History

Abstract

Power consumption of digital systems may increasesignificantly during testing. In this paper, we propose anovel low power/energy Built-In Self Test (BIST) strategybased on circuit partitioning. The strategy consists inpartitioning the original circuit into structural subcircuitsso that each subcircuit can be successively tested throughdifferent BIST sessions. In partitioning the circuit andplanning the test session, the switching activity in a timeinterval (i.e. the average power) as well as the peak powerconsumption are minimized. Moreover, the total energyconsumption during BIST is also reduced since the testlength required to test the subcircuits is not so far from thetest length for the original circuit. The proposed strategycan be applied to either test-per-scan or test-per-clockBIST schemes by slightly modifying conventional TPGstructures as illustrated in this paper. Results on ISCAScircuits show that average power reduction of up to 62%,peak power reduction of up to 57%, and energy reductionof up to 82% can be achieved at a very low area cost interms of area overhead and with almost no penalty on thecircuit timing.

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Cited By

Chan TLouis ATang ZZhang C(2018)Spectral Properties of Hypergraph Laplacian and Approximation AlgorithmsJournal of the ACM10.1145/317812365:3(1-48)Online publication date: 5-Mar-2018
https://dl.acm.org/doi/10.1145/3178123
Li NDubrova ECarlsson GNebel WAtienza D(2015)A scan partitioning algorithm for reducing capture power of delay-fault LBISTProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755944(842-847)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2755944
Louis AServedio RRubinfeld R(2015)Hypergraph Markov Operators, Eigenvalues and Approximation AlgorithmsProceedings of the forty-seventh annual ACM symposium on Theory of Computing10.1145/2746539.2746555(713-722)Online publication date: 14-Jun-2015
https://dl.acm.org/doi/10.1145/2746539.2746555
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Index Terms

Low Power BIST Design by Hypergraph Partitioning: Methodology and Architectures
1. Hardware

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cover image Guide Proceedings

ITC '00: Proceedings of the 2000 IEEE International Test Conference

October 2000

ISBN:0780365461

Copyright © Copyright (c) 2000 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

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IEEE Computer Society

United States

Publication History

Published: 03 October 2000

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Cited By

Chan TLouis ATang ZZhang C(2018)Spectral Properties of Hypergraph Laplacian and Approximation AlgorithmsJournal of the ACM10.1145/317812365:3(1-48)Online publication date: 5-Mar-2018
https://dl.acm.org/doi/10.1145/3178123
Li NDubrova ECarlsson GNebel WAtienza D(2015)A scan partitioning algorithm for reducing capture power of delay-fault LBISTProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755944(842-847)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2755944
Louis AServedio RRubinfeld R(2015)Hypergraph Markov Operators, Eigenvalues and Approximation AlgorithmsProceedings of the forty-seventh annual ACM symposium on Theory of Computing10.1145/2746539.2746555(713-722)Online publication date: 14-Jun-2015
https://dl.acm.org/doi/10.1145/2746539.2746555
Chen ZChakrabarty KXiang DScheffer LPhillips JHu A(2010)MVPProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133459(149-154)Online publication date: 7-Nov-2010
https://dl.acm.org/doi/10.5555/2133429.2133459
Wang Y(2009)A low power consumption BIST testing technology based on heavy inputProceedings of the 3rd international conference on Anti-Counterfeiting, security, and identification in communication10.5555/1719110.1719190(340-342)Online publication date: 20-Aug-2009
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Elshoukry MTehranipoor MRavikumar C(2007)A critical-path-aware partial gating approach for test power reductionACM Transactions on Design Automation of Electronic Systems10.1145/1230800.123080912:2(17-es)Online publication date: 1-Apr-2007
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Girard P(2002)Survey of Low-Power Testing of VLSI CircuitsIEEE Design & Test10.1109/MDT.2002.100380219:3(82-92)Online publication date: 1-May-2002
https://dl.acm.org/doi/10.1109/MDT.2002.1003802
Xu LSun YChen H(2001)Scan Array Solution for Testing Power and Testing TimeProceedings of the 2001 IEEE International Test Conference10.5555/839296.843876Online publication date: 30-Oct-2001
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