Article

A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores

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S. PravossoudovitchAuthors Info & Claims

ATS '01: Proceedings of the 10th Asian Test Symposium

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Published: 19 November 2001 Publication History

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Abstract

Test power is now a big concern in large System-on-Chip designs. In this paper, we present a novel approach for minimizing power consumption during scan testing of integrated circuits or embedded cores. The proposed low power technique is based on a gated clock scheme for the scan path and the clock tree feeding the scan path. The idea is to reduce the clock rate on scan cells during shift operations without increasing the test time. Numerous advantages can be found in applying such a technique.

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Naeini MDass SOoi CYoneda TInoue M(2017)An integrated DFT solution for power reduction in scan test applications by low power gating scan cellIntegration, the VLSI Journal10.1016/j.vlsi.2016.12.00957:C(108-124)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.12.009
Karmakar RChattopadhyay S(2017)Temperature and data size trade-off in dictionary based test data compressionIntegration, the VLSI Journal10.1016/j.vlsi.2016.11.00257:C(20-33)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.11.002
Juneja KPatel DImmadi RSingh BNaudet SAgarwal PVirazel AGirard P(2016)An Effective Power-Aware At-Speed Test Methodology for IP Qualification and CharacterizationJournal of Electronic Testing: Theory and Applications10.1007/s10836-016-5621-132:6(721-733)Online publication date: 1-Dec-2016
https://dl.acm.org/doi/10.1007/s10836-016-5621-1
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A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores
1. Hardware
  1. Emerging technologies

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ATS '01: Proceedings of the 10th Asian Test Symposium

November 2001

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IEEE Computer Society

United States

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Published: 19 November 2001

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Naeini MDass SOoi CYoneda TInoue M(2017)An integrated DFT solution for power reduction in scan test applications by low power gating scan cellIntegration, the VLSI Journal10.1016/j.vlsi.2016.12.00957:C(108-124)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.12.009
Karmakar RChattopadhyay S(2017)Temperature and data size trade-off in dictionary based test data compressionIntegration, the VLSI Journal10.1016/j.vlsi.2016.11.00257:C(20-33)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.11.002
Juneja KPatel DImmadi RSingh BNaudet SAgarwal PVirazel AGirard P(2016)An Effective Power-Aware At-Speed Test Methodology for IP Qualification and CharacterizationJournal of Electronic Testing: Theory and Applications10.1007/s10836-016-5621-132:6(721-733)Online publication date: 1-Dec-2016
https://dl.acm.org/doi/10.1007/s10836-016-5621-1
Wu YChao M(2010)Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test CubesACM Transactions on Design Automation of Electronic Systems10.1145/1870109.187011916:1(1-29)Online publication date: 1-Nov-2010
https://dl.acm.org/doi/10.1145/1870109.1870119
Alpaslan EHuang YLin XCheng WDworak J(2010)On reducing scan shift activity at RTLIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.204905729:7(1110-1120)Online publication date: 1-Jul-2010
https://dl.acm.org/doi/10.1109/TCAD.2010.2049057
Tzeng CHuang SBenini LDe Micheli GAl-Hashimi BMueller W(2009)QC-fillProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874896(1142-1147)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874896
Czysz DKassab MLin XMrugalski GRajski JTyszer J(2009)Low-power scan operation in test compression environmentIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.203044528:11(1742-1755)Online publication date: 1-Nov-2009
https://dl.acm.org/doi/10.1109/TCAD.2009.2030445
Tzeng CHuang S(2009)QC-fillIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.203035328:11(1756-1766)Online publication date: 1-Nov-2009
https://dl.acm.org/doi/10.1109/TCAD.2009.2030353
Xiang DHu DXu QOrailoglu A(2009)Low-power scan testing for test data compression using a routing-driven scan architectureIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.201877528:7(1101-1105)Online publication date: 1-Jul-2009
https://dl.acm.org/doi/10.1109/TCAD.2009.2018775
Li YMakar SMitra SSciuto D(2008)CASPProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403590(885-890)Online publication date: 10-Mar-2008
https://dl.acm.org/doi/10.1145/1403375.1403590
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