Article

Testing the Printability of VLSI Layouts

Authors:

Rui Martins,

H. KirchauerAuthors Info & Claims

SBCCI '01: Proceedings of the 14th symposium on Integrated circuits and systems design

Page 186

Published: 10 September 2001 Publication History

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Abstract

Abstract: Lithography has always been a key technology process step for the semiconductor industry. Clearly, both circuit speed and complexity (density) rely on the lithographic minimum printable feature size. For industry, besides pure resolution, throughput is also of paramount importance. For this reason optical lithography has been used ubiquitously for large scale manufacturing, as it guarantees a high wafer throughput. This paper presents an easy to use CAD tool capable of checking whether a VLSI layout can (or not) be correctly printed using a given imaging system. The tool is built upon a layout editor capable of handling phase-shift masks and a lithographic simulator that are tightly integrated.

Testing the Printability of VLSI Layouts
1. Applied computing
  1. Physical sciences and engineering
2. Hardware

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Published In

SBCCI '01: Proceedings of the 14th symposium on Integrated circuits and systems design

September 2001

ISBN:0769513336

Publisher

IEEE Computer Society

United States

Publication History

Published: 10 September 2001

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SBCCI01

Sponsor:

SIGDA

SBCCI01: Symposium on Integrated Circuits and Systems Design

September 10 - 15, 2001

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Overall Acceptance Rate 133 of 347 submissions, 38%

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Recommendations

Printability of defects in Talbot lithography

A Study of Screen Printability of UV Soy Ink on Plastics

Reducing EPL Alignment Errors for Large VLSI Layouts

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