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10.5555/882503.884946guideproceedingsArticle/Chapter ViewAbstractPublication PagesConference Proceedingsacm-pubtype
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Compact test generation for bridging faults under I/sub DDQ/ testing

Published: 30 April 1995 Publication History

Abstract

Abstract: We propose a procedure to generate compact test sets for bridging faults under I/sub DDQ/ testing. Several techniques are employed to achieve compact test sets. Heuristics developed for stuck-at faults are shown to be effective in this context. The techniques especially designed for bridging faults are based on the observation that the yet-undetected faults can be represented using sets of lines and that a minimum test set size is obtained if the line sets representing yet-undetected faults are halved with every additional test vector. Logic blocks called bit-adders allow the partitioning of the line sets using a test generator for stuck-at faults, without having to determine in advance how the lines in a given set will be divided. Thus partitioning can be performed in a cost effective way for any line set size. Experimental results show that the test sets generated by the proposed procedure are smaller than those obtained by previously proposed procedures.

Cited By

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  • (2005)Dynamic Test Compaction for Bridging FaultsProceedings of the 6th International Symposium on Quality of Electronic Design10.1109/ISQED.2005.48(250-255)Online publication date: 21-Mar-2005
  • (2000)Fault models and test generation for IDDQ testingProceedings of the 2000 Asia and South Pacific Design Automation Conference10.1145/368434.368773(509-514)Online publication date: 28-Jan-2000
  • (2000)Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential CircuitsJournal of Electronic Testing: Theory and Applications10.1023/A:100836043095916:5(443-451)Online publication date: 1-Oct-2000
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        cover image Guide Proceedings
        VTS '95: Proceedings of the 13th IEEE VLSI Test Symposium
        April 1995
        ISBN:0818670002

        Publisher

        IEEE Computer Society

        United States

        Publication History

        Published: 30 April 1995

        Author Tags

        1. CMOS logic circuits
        2. I/sub DDQ/ testing
        3. bit-adders
        4. bridging faults
        5. compact test generation
        6. fault location
        7. integrated circuit testing
        8. logic partitioning
        9. logic testing
        10. partitioning
        11. stuck-at faults

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        Cited By

        View all
        • (2005)Dynamic Test Compaction for Bridging FaultsProceedings of the 6th International Symposium on Quality of Electronic Design10.1109/ISQED.2005.48(250-255)Online publication date: 21-Mar-2005
        • (2000)Fault models and test generation for IDDQ testingProceedings of the 2000 Asia and South Pacific Design Automation Conference10.1145/368434.368773(509-514)Online publication date: 28-Jan-2000
        • (2000)Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential CircuitsJournal of Electronic Testing: Theory and Applications10.1023/A:100836043095916:5(443-451)Online publication date: 1-Oct-2000
        • (2000)Compaction of IDDQ Test Sequence Using Reassignment MethodJournal of Electronic Testing: Theory and Applications10.1023/A:100834343197516:3(243-249)Online publication date: 1-Jun-2000
        • (1996)Fast Algorithms for Computer IDDQ Tests for Combination CircuitsProceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication10.5555/525699.834801Online publication date: 3-Jan-1996
        • (1996)On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic CircuitsProceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication10.5555/525699.834721Online publication date: 3-Jan-1996
        • (1996)Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational CircuitsIEEE Transactions on Computers10.1109/12.54370745:10(1131-1140)Online publication date: 1-Oct-1996
        • (1995)On adaptive diagnostic test generationProceedings of the 1995 IEEE/ACM international conference on Computer-aided design10.5555/224841.224878(181-184)Online publication date: 1-Dec-1995
        • (1995)IDDQ Test and Diagnosis of CMOS CircuitsIEEE Design & Test10.1109/54.49123912:4(60-67)Online publication date: 1-Dec-1995

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