- Authors:
- A. Agarwal,
- B. H. Lim,
- D. Kranz,
- J. Kubiatowicz
Processors in large-scale multiprocessors must be able to tolerate large communication latencies and synchronization delays. This paper describes the architecture of a rapid-context-switching processor called APRIL with support for fine-grain threads and synchronization. APRIL achieves high single-thread performance and supports virtual dynamic threads. A commercial RISC-based implementation of APRIL and a run-time software system that can switch contexts in about 10 cycles is described. Measurements taken for several parallel applications on an APRIL simulator show that the overhead for supporting parallel tasks based on futures is reduced by a factor of two over a corresponding implementation on the Encore Multimax. The scalability of a multiprocessor based on APRIL is explored using a performance model. We show that the SPARC-based implementation of APRIL can achieve close to 80% processor utilization with as few as three resident threads per processor in a large-scale cache-based machine with an average base network latency of 55 cycles.
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Cited By
Luque C, Moreto M, Cazorla F and Valero M (2013). Fair CPU time accounting in CMP+SMT processors, ACM Transactions on Architecture and Code Optimization (TACO), 9:4, (1-25), Online publication date: 1-Jan-2013.- Čakarević V, Radojković P, Verdú J, Pajuelo A, Cazorla F, Nemirovsky M and Valero M Characterizing the resource-sharing levels in the UltraSPARC T2 processor Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, (481-492)
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