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Cache Performance of the SPEC Benchmark SuiteJanuary 1991
1991 Technical Report
Publisher:
  • University of California at Berkeley
  • Computer Science Division 571 Evans Hall Berkeley, CA
  • United States
Published:01 January 1991
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Abstract

The SPEC benchmark suite consists of ten public-domain, non-trivial programs that are widely used to measure the performance of computer systems, particularly those in the Unix workstation market. These benchmarks were expressly chosen to repre sent real-world applications and were intended to be large enough to stress the computational and memory system resources of current-generation machines. The extent to which the SPECmark (the figure of merit obtained from running the SPEC benchmarks under certain specified conditions) accurately represent s performance with live real workloads is not well established; in particular, there is some question whether the memory referencing behavior (cache performance) is appropriate. In this paper, we present measurements of miss ratios for the entire set of SPEC benchmarks for a variety of CPU cache configurations; this study extends earlier work that measured only the performance of the integer (C) SPEC benchmarks. We find that inst ruction cache miss ratios are generally very low, and that data cache miss ratios for the integer benchmarks are also quite low. Data cache miss ratios for the floating point benchmarks are more in line with published measurements for real workloads. We b elieve that the discrepancy between the SPEC benchmark miss ratios and those observed elsewhere is partially due to the fact that the SPEC benchmarks are all almost exclusively user state CPU benchmarks run until completion as the single active user process. We therefore believe that SPECmark performance levels may not reflect system performance when there is multiprogramming, time sharing and/or significant operating systems activity.

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  3. Megiddo N and Modha D ARC Proceedings of the 2nd USENIX conference on File and storage technologies, (9-9)
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  5. Hartstein A and Puzak T The optimum pipeline depth for a microprocessor Proceedings of the 29th annual international symposium on Computer architecture, (7-13)
  6. Pereira P, Heutte L and Lecourtier Y (2019). Source-to-Source Instrumentation for the Optimization of an Automatic Reading System, The Journal of Supercomputing, 18:1, (89-104), Online publication date: 1-Jan-2001.
  7. Westerholz K, Honal S, Plankl J and Hafer C Improving performance by cache driven memory management Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
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    Gee J and Smith A The effectiveness of caches for vector processors Proceedings of the 8th international conference on Supercomputing, (333-343)
  9. Larus J (1993). Loop-Level Parallelism in Numeric and Symbolic Programs, IEEE Transactions on Parallel and Distributed Systems, 4:7, (812-826), Online publication date: 1-Jul-1993.
Contributors
  • Sun Microsystems
  • Microsoft Corporation
  • University of California, Berkeley

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