Representation and detection of concurrency using ordering-matrices.
- Author:
- Garold Stephen Tjaden
Abstract
No abstract available.
Cited By
Uht A (2002). Disjoint Eager Execution, ACM SIGARCH Computer Architecture News, 30:1, (12-14), Online publication date: 1-Mar-2002.- Uht A (2019). Concurrency Extraction Via Hardware Methods Executing the Static Instruction Stream, IEEE Transactions on Computers, 41:7, (826-841), Online publication date: 1-Jul-1992.
- Uht A (2019). A Theory of Reduced and Minimal Procedural Dependencies, IEEE Transactions on Computers, 40:6, (681-692), Online publication date: 1-Jun-1991.
- Uht A and Kolen J (1988). On the combination of hardware and software concurrency extraction methods, ACM SIGMICRO Newsletter, 19:1-2, (53-57), Online publication date: 1-Jun-1988.
- Jacobs J, Uht A and Ord R Modeling the effects of instruction queue loading on a static instruction stream micro-architecture Proceedings of the 21st annual workshop on Microprogramming and microarchitecture, (11-20)
- Uht A, Polychronopoulos C and Kolen J On the combination of hardware and software concurrency extraction methods Proceedings of the 20th annual workshop on Microprogramming, (133-141)
- Acosta R, Kjelstrup J and Torng H (1986). An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors, IEEE Transactions on Computers, 35:9, (815-828), Online publication date: 1-Sep-1986.
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