Browse Theses

Circuit partitioning is an important problem in the computer-aided design (CAD) of very large scale integrated circuits (VLSI). Partitioning techniques are used to address the increasing complexity of VLSI design in any top-down hierarchical approach, and have a great impact on system performance as designs become more interconnect-dominated and I/O pin constrained.

In this dissertation, we study some of the essential partitioning problems in CAD for VLSI. We develop partitioning algorithms for multi-chip design, FPGA design, reconfigurable computing, and hardware/software codesign.

The problem of multi-way partitioning with area and pin constraints has important applications in multi-chip and multi-FPGA design. We present algorithm FBB-MW, an extension of the network flow based bipartitioning algorithm FBB, for multi-way partitioning with area and pin constraints.

The new generation of FPGAs are becoming more heterogeneous in terms of resources available, and impose complex resource constraint for the partitioning process. We present an efficient algorithm to optimally check whether a circuit is feasible for a given set of resources, and then integrate the feasibility checking into the FM based heuristic for finding a feasible min-cut.

Dynamically reconfigurable FPGAs have the potential to dramatically increase logic density by sharing the same FPGA device in a time-multiplexed fashion. The partitioning for dynamically reconfigurable FPGAs must satisfy the precedence constraint and timing constraint, while minimizing the communication cost. We present a net modeling method for exactly modeling the precedence constraint and the communication cost. We develop efficient network flow based multi-way partitioning algorithms based on two different dynamically reconfigurable FPGA architectures. Experiments show that our algorithms outperform the previous approaches by a big margin. Moreover, we optimally solve the schedule compression problem for improving the partitioning quality for dynamically reconfigurable FPGAs.

Heterogeneous hardware/software architecture provides an effective design solution for the cost and performance of the target system. We present an integrated partitioning and scheduling technique for hardware/software codesign.