A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture

Network on Chip (NoC) is a new paradigm fordesigning core based System on Chip which supports highdegree of reusability and is scalable. In this paper wedescribe an efficient two-step genetic algorithm that hasbeen used to build a tool for mapping an application,described by a parameterized task graph, on to a NoCarchitecture with a two dimensional mesh of switches as acommunication backbone. The computational resources inNoC consists of a set of heterogenous IP cores. Ouralgorithm finds a mapping of the vertices of the taskgraph to available cores so that the overall execution timeof the task graph is minimized. We have developed a NoCarchitecture specific communication delay model toestimate the execution time. Our algorithm is able tohandle large task graphs and provide near optimalmapping in a few minutes on a PC platform. Our tool alsoprovides facilities for specifying NoC architecture,generation and viewing synthetic task graphs and viewingthe progress of the genetic algorithm as it converges to asolution.