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A Locating Method for Reliability-Critical Gates with a Parallel-Structured Genetic Algorithm

Published: 01 September 2019 Publication History

Abstract

The reliability allowance of circuits tends to decrease with the increase of circuit integration and the application of new technology and materials, and the hardening strategy oriented toward gates is an effective technology for improving the circuit reliability of the current situations. Therefore, a parallel-structured genetic algorithm (GA), PGA, is proposed in this paper to locate reliability-critical gates to successfully perform targeted hardening. Firstly, we design a binary coding method for reliability-critical gates and build an ordered initial population consisting of dominant individuals to improve the quality of the initial population. Secondly, we construct an embedded parallel operation loop for directional crossover and directional mutation to compensate for the deficiency of the poor local search of the GA. Thirdly, for combination with a diversity protection strategy for the population, we design an elitism retention based selection method to boost the convergence speed and avoid being trapped by a local optimum. Finally, we present an ordered identification method oriented toward reliability-critical gates using a scoring mechanism to retain the potential optimal solutions in each round to improve the robustness of the proposed locating method. The simulation results on benchmark circuits show that the proposed method PGA is an efficient locating method for reliability-critical gates in terms of accuracy and convergence speed.

References

[1]
Xiao J, Jiang J H, Li X X et al. A novel trust evaluation method for logic circuits in IoT applications based on the E-PTM model. IEEE Access, 2018, 6: 35683-35696.
[2]
Zhang Y, Li H W, Li X W. Automatic test program generation using executing-trace-based constraint extraction for embedded processors. IEEE Transactions on Very Large Scale Integration Systems, 2013, 21(7): 1220-1233.
[3]
Srinivasu B, Sridharan K. A transistor-level probabilistic approach for reliability analysis of arithmetic circuits with applications to emerging technologies. IEEE Transactions on Reliability, 2017, 66(2): 440-457.
[4]
Xiao J, Lee W, Jiang J H et al. Sensitivity evaluation of input vectors with masking effects in digital circuits. Chinese Journal of Computers, 2018, 41(10): 2282-2294. (in Chinese)
[5]
Bickford J, Habib N, Li B et al. Integrated circuit chip reliability qualification using a sample-specific expected fail rate. United States Patent, http://www.freepatentsonline.com/9639645.pdf, May 2019.
[6]
Han J, Hao C, Liang J H et al. A stochastic computational approach for accurate and efficient reliability evaluation. IEEE Transactions on Computers, 2014, 63(6): 1336-1350.
[7]
Mittal S, Vetter J S. A survey of techniques for modeling and improving reliability of computing systems. IEEE Transactions on Parallel and Distributing Systems, 2016, 27(4): 1226-1238.
[8]
Xiao J, Lee W, Jiang J H et al. Circuit reliability estimation based on an iterative PTM model with hybrid coding. Microelectronics Journal, 2016, 52: 117-123.
[9]
Bernardini A, Schlichtmann U. Symbolic fault modeling and model counting for the identification of critical gates in digital circuits. In Proc. IEEE GMM/ITG/ GI-Symposium Reliability by Design, Sept. 2015, pp.15-22.
[10]
Xiao J, Lou J G, Jiang J H et al. Blockchain architecture reliability-based measurement for circuit unit importance. IEEE Access, 2018, 6: 15326-15334.
[11]
Ibrahim W. Identifying the worst reliability input vectors and the associated critical logic gates. IEEE Transactions on Computers, 2016, 65(6): 1748-1760.
[12]
Ibrahim W, Beiu V, Amer H. Why should we care about input vectors? In Proc. the 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, Jun. 2009, Article No. 60.
[13]
Janssen H. Monte-Carlo based uncertainty analysis: Sampling efficiency and sampling convergence. Reliability Engineering & System Safety, 2013, 109: 123-132.
[14]
Rubinstein R Y, Kroese D P. Simulation and the Monte Carlo Method (3rd edition). Wiley, 2016.
[15]
Han J, Chen H, Boykin E et al. Reliability evaluation of logic circuits using probabilistic gate models. Microelectronics Reliability, 2011, 51(2): 468-476.
[16]
Tang A, Jha N K. GenFin: Genetic algorithm-based multiobjective statistical logic circuit optimization using incremental statistical analysis. IEEE Transactions on Very Large Scale Integration Systems, 2016, 24(3): 1126-1139.
[17]
Srinivas M, Patnaik L. On generating optimal signal probabilities for random tests: A genetic approach. VLSI Design, 1996, 4(3): 207-215.
[18]
Nagamani A, Nayak A, Nanditha N et al. A genetic algorithm based heuristic method for test set generation in reversible circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018, 37(2): 324-336.
[19]
Liliakadri R, Boctor F. An efficient genetic algorithm to solve the resource-constrained project scheduling problem with transfer times: The single mode case. European Journal of Operational Research, 2018, 265(2): 454-462.
[20]
Kvassay M, Zaitseva E, Levashenko V et al. Reliability analysis of multiple-outputs logic circuits based on structure function approach. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017, 36(3): 398-411.
[21]
Xiao J, Lou J G, Jiang J H. A fast and effective sensitivity calculation method for circuit input vectors. IEEE Transactions on Reliability. https://doi.org/10.1109/TR.2019.2897455.
[22]
Corus D, Dang D, Eremeev A et al. Level-based analysis of genetic algorithms and other search processes. IEEE Transactions on Evolutionary Computation, 2018, 22(5): 707-719.
[23]
Bito J, Jeong S, Tentzeris M. A novel heuristic passive and active matching circuit design method for wireless power transfer to moving objects. IEEE Transactions on Microwave Theory Techniques, 2017, 65(4): 1094-1102.
[24]
Ye Z, Li Z, Xie M. Some improvements on adaptive genetic algorithms for reliability-related applications. Reliability Engineering & System Safety, 2017, 95(2): 120-126.
[25]
Silver D, Huang A, Maddison C J et al. Mastering the game of Go with deep neural networks and tree search. Nature, 2016, 529(7587): 484-489.
[26]
Sivaraj R, Ravichandran D. A review of selection methods in genetic algorithms. International Journal of Engineering Science and Technology, 2011, 3(5): 3792-3797.
[27]
Pandey H M, Shukla A, Chaudhary A et al. Evaluation of genetic algorithm’s selection methods. In Proc. the 3rd International Conference on Information Systems Design and Intelligent Applications, January 2016, pp.731-738.
[28]
Krishnaswamy S, Viamontes G F, Markov I L et al. Accurate reliability evaluation and enhancement via probabilistic transfer matrices. In Proc. the 2005 Design, Automation and Test in Europe, March 2005, pp.282-287.
[29]
Ji Z, Xia Q, Meng G. A review of parameter learning methods in Bayesian network. In Proc. the 11th International Conference on Intelligent Computing, Part III, Aug. 2015, pp.3-12.
[30]
Shahani A, Natu N, Badami A. A Genetic Algorithm for VLSI Floorplanning: An Intuitive Approach to Optimisation and Miniaturisation of IC. LAP LAMBERT Academic Publishing, 2012.

Cited By

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  • (2024)ARA-RCIV: Identifying Reliability-Critical Input Vectors of Logic Circuits Based on the Association Rules Analysis ApproachIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.337246143:8(2479-2492)Online publication date: 1-Aug-2024
  • (2022)Identifying Reliability-Critical Primary Inputs of Combinational Circuits Based on the Model of Gate-Sensitive AttributesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.314219441:11(4708-4720)Online publication date: 1-Nov-2022
  • (2022)Accelerating stochastic‐based reliability estimation for combinational circuits at RTL using GPU parallel computingInternational Journal of Intelligent Systems10.1002/int.2294037:11(8309-8326)Online publication date: 9-Jun-2022

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          Published In

          cover image Journal of Computer Science and Technology
          Journal of Computer Science and Technology  Volume 34, Issue 5
          Sep 2019
          228 pages

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          Springer-Verlag

          Berlin, Heidelberg

          Publication History

          Published: 01 September 2019

          Author Tags

          1. gate-level circuit reliability
          2. locating reliability-critical gate
          3. parallel-structured genetic algorithm
          4. directing strategy
          5. scoring mechanism

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          View all
          • (2024)ARA-RCIV: Identifying Reliability-Critical Input Vectors of Logic Circuits Based on the Association Rules Analysis ApproachIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.337246143:8(2479-2492)Online publication date: 1-Aug-2024
          • (2022)Identifying Reliability-Critical Primary Inputs of Combinational Circuits Based on the Model of Gate-Sensitive AttributesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.314219441:11(4708-4720)Online publication date: 1-Nov-2022
          • (2022)Accelerating stochastic‐based reliability estimation for combinational circuits at RTL using GPU parallel computingInternational Journal of Intelligent Systems10.1002/int.2294037:11(8309-8326)Online publication date: 9-Jun-2022
          • (2020)A Location Method for Reliability-Critical Paths Based on Monte Carlo Search TreeMachine Learning for Cyber Security10.1007/978-3-030-62463-7_10(100-114)Online publication date: 8-Oct-2020

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