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Benchmark Synthesis Using the LRU Cache Hit Function

Published: 01 June 1988 Publication History

Abstract

The LRU cache hit function is used as a general characterization of locality of reference to address the synthesis question of whether benchmarks can be created that have a required locality of reference. Several results are given that show circumstances under which this synthesis can or cannot be achieved. An additional characterization called the warm-start cache hit function is introduced and shown to be efficiently computable. The operations of repetition and replication are used to form new programs, and their characteristics are derived. Using these operations, a general benchmark synthesis technique is obtained and demonstrated with an example.

References

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Cited By

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  • (2023)EMISSARY: Enhanced Miss Awareness Replacement Policy for L2 Instruction CachingProceedings of the 50th Annual International Symposium on Computer Architecture10.1145/3579371.3589097(1-13)Online publication date: 17-Jun-2023
  • (2014)A methodology for automatic generation of executable communication specifications from parallel MPI applicationsACM Transactions on Parallel Computing10.1145/26602491:1(1-30)Online publication date: 3-Oct-2014
  • (2012)Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-BenchmarksProceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2012.27(199-211)Online publication date: 1-Dec-2012
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Published In

cover image IEEE Transactions on Computers
IEEE Transactions on Computers  Volume 37, Issue 6
June 1988
136 pages

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IEEE Computer Society

United States

Publication History

Published: 01 June 1988

Author Tags

  1. LRU cache hit function
  2. benchmark synthesis
  3. computer testing
  4. locality of reference
  5. performance evaluation.
  6. warm-start cache hit function

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View all
  • (2023)EMISSARY: Enhanced Miss Awareness Replacement Policy for L2 Instruction CachingProceedings of the 50th Annual International Symposium on Computer Architecture10.1145/3579371.3589097(1-13)Online publication date: 17-Jun-2023
  • (2014)A methodology for automatic generation of executable communication specifications from parallel MPI applicationsACM Transactions on Parallel Computing10.1145/26602491:1(1-30)Online publication date: 3-Oct-2014
  • (2012)Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-BenchmarksProceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2012.27(199-211)Online publication date: 1-Dec-2012
  • (2011)MAximum Multicore POwer (MAMPO)Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis10.1145/2063384.2063455(1-12)Online publication date: 12-Nov-2011
  • (2008)Distilling the essence of proprietary workloads into miniature benchmarksACM Transactions on Architecture and Code Optimization10.1145/1400112.14001155:2(1-33)Online publication date: 3-Sep-2008
  • (2008)Accurate memory signatures and synthetic address traces for HPC applicationsProceedings of the 22nd annual international conference on Supercomputing10.1145/1375527.1375536(36-45)Online publication date: 7-Jun-2008
  • (2005)Improved automatic testcase synthesis for performance model validationProceedings of the 19th annual international conference on Supercomputing10.1145/1088149.1088164(111-120)Online publication date: 20-Jun-2005
  • (2004)Issues and Challenges in the Performance Analysis of Real Disk ArraysIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2004.915:6(559-574)Online publication date: 1-Jun-2004
  • (1992)Synthetic Traces for Trace-Driven Simulation of Cache MemoriesIEEE Transactions on Computers10.1109/12.13555241:4(388-410)Online publication date: 1-Apr-1992

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