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Packet classification using binary content addressable memory

Published: 01 June 2016 Publication History

Abstract

Packet classification is the core mechanism that enables many networking devices. Although using ternary content addressable memory (TCAM) to perform high-speed packet classification has become the widely adopted solution, TCAM is very expensive, has limited capacity, consumes large amounts of power, and generates tremendous amounts of heat because of their extremely dense and parallel circuitry. In this paper, we propose the first packet classification scheme that uses binary CAM (BCAM). BCAM is similar to TCAM except that in BCAM, every bit has only two possible states: 0 or 1; in contrast, in TCAM, every bit has three possible states: 0, 1, or * (don't care). Because of the high complexity in implementing the extra "don't care" state, TCAM has much higher circuit density than BCAM. As the power consumption, heat generation, and price grow non-linearly with circuit density, BCAM consumes much less power, generates much less heat, and costs much less money than TCAM. Our BCAM-based packet classification scheme is built on two key ideas. First, we break a multi-dimensional lookup into a series of 1-D lookups. Second, for each 1-D lookup, we convert the ternary matching problem into a binary string exact matching problem. To speed up the lookup process, we propose a number of optimization techniques, including skip lists, free expansion, minimizing maximum lookup time, minimizing average lookup time, and lookup short circuiting. We evaluated our BCAM scheme on 17 real-life packet classifiers. On these classifiers, our BCAM scheme requires roughly five times fewer CAM bits than the traditional TCAM-based scheme. The penalty is a throughput that is roughly four times less.

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  • (2023)NeuroLPM - Scaling Longest Prefix Match Hardware with Neural NetworksProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3623769(886-899)Online publication date: 28-Oct-2023
  • (2023)Using FPGA-based content-addressable memory for mnemonics instruction searching in assembler designThe Journal of Supercomputing10.1007/s11227-023-05357-279:15(17386-17418)Online publication date: 7-May-2023
  • (2022)Hardware-based multi-match packet classification in NIDS: an overview and novel extensions for improving the energy efficiency of TCAM-based classifiersThe Journal of Supercomputing10.1007/s11227-022-04377-878:11(13086-13121)Online publication date: 1-Jul-2022
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Published In

cover image IEEE/ACM Transactions on Networking
IEEE/ACM Transactions on Networking  Volume 24, Issue 3
June 2016
638 pages
ISSN:1063-6692
  • Editor:
  • R. Srikant
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IEEE Press

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Published: 01 June 2016
Published in TON Volume 24, Issue 3

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  1. binary content addressable memory (bcam)
  2. packet classification

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  • (2023)NeuroLPM - Scaling Longest Prefix Match Hardware with Neural NetworksProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3623769(886-899)Online publication date: 28-Oct-2023
  • (2023)Using FPGA-based content-addressable memory for mnemonics instruction searching in assembler designThe Journal of Supercomputing10.1007/s11227-023-05357-279:15(17386-17418)Online publication date: 7-May-2023
  • (2022)Hardware-based multi-match packet classification in NIDS: an overview and novel extensions for improving the energy efficiency of TCAM-based classifiersThe Journal of Supercomputing10.1007/s11227-022-04377-878:11(13086-13121)Online publication date: 1-Jul-2022
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  • (2019)A Novel Rule Mapping on TCAM for Power Efficient Packet ClassificationACM Transactions on Design Automation of Electronic Systems10.1145/332810324:5(1-23)Online publication date: 7-Jun-2019
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