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Incrementally parallelizing database transactions with thread-level speculation

Published: 10 March 2008 Publication History

Abstract

With the advent of chip multiprocessors, exploiting intratransaction parallelism in database systems is an attractive way of improving transaction performance. However, exploiting intratransaction parallelism is difficult for two reasons: first, significant changes are required to avoid races or conflicts within the DBMS; and second, adding threads to transactions requires a high level of sophistication from transaction programmers. In this article we show how dividing a transaction into speculative threads solves both problems—it minimizes the changes required to the DBMS, and the details of parallelization are hidden from the transaction programmer. Our technique requires a limited number of small, localized changes to a subset of the low-level data structures in the DBMS. Through this method of incrementally parallelizing transactions, we can dramatically improve performance: on a simulated four-processor chip-multiprocessor, we improve the response time by 44--66% for three of the five TPC-C transactions, assuming the availability of idle processors.

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cover image ACM Transactions on Computer Systems
ACM Transactions on Computer Systems  Volume 26, Issue 1
February 2008
153 pages
ISSN:0734-2071
EISSN:1557-7333
DOI:10.1145/1328671
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 10 March 2008
Accepted: 01 November 2007
Revised: 01 August 2007
Received: 01 July 2006
Published in TOCS Volume 26, Issue 1

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Author Tags

  1. Thread-level speculation
  2. chip-multiprocessing
  3. incremental parallelization
  4. optimistic concurrency

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