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Multiple-block ahead branch predictors

Authors:

Stéphan Jourdan,

Pascal Sainrat,

Pierre MichaudAuthors Info & Claims

ACM SIGOPS Operating Systems Review, Volume 30, Issue 5

Pages 116 - 127

https://doi.org/10.1145/248208.237169

Published: 01 September 1996 Publication History

Abstract

A basic rule in computer architecture is that a processor cannot execute an application faster than it fetches its instructions. This paper presents a novel cost-effective mechanism called the two-block ahead branch predictor. Information from the current instruction block is not used for predicting the address of the next instruction block, but rather for predicting the block following the next instruction block.This approach overcomes the instruction fetch bottle-neck exhibited by wide-dispatch "brainiac" processors by enabling them to efficiently predict addresses of two instruction blocks in a single cycle. Furthermore, pipelining the branch prediction process can also be done by means of our predictor for "speed demon" processors to achieve higher clock rate or to improve the prediction accuracy by means of bigger prediction structures.Moreover, and unlike the previously-proposed multiple predictor schemes, multiple-block ahead branch predictors can use any of the branch prediction schemes to perform the very accurate predictions required to achieve high-performance on superscalar processors.

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Cited By

Tran KCarlson TKoukos KSjalander MSpiliopoulos VKaxiras SJimborean A(2018)Static Instruction Scheduling for High Performance on Limited HardwareIEEE Transactions on Computers10.1109/TC.2017.276964167:4(513-527)Online publication date: 1-Apr-2018
https://doi.org/10.1109/TC.2017.2769641
Tran KCarlson TKoukos KSjälander MSpiliopoulos VKaxiras SJimborean AReddi VSmith ATang L(2017)Clairvoyance: look-ahead compile-time schedulingProceedings of the 2017 International Symposium on Code Generation and Optimization10.5555/3049832.3049852(171-184)Online publication date: 4-Feb-2017
https://dl.acm.org/doi/10.5555/3049832.3049852
Tran KCarlson TKoukos KSjalander MSpiliopoulos VKaxiras SJimborean A(2017)Clairvoyance: Look-ahead compile-time scheduling2017 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)10.1109/CGO.2017.7863738(171-184)Online publication date: Feb-2017
https://doi.org/10.1109/CGO.2017.7863738
Show More Cited By

Index Terms

Multiple-block ahead branch predictors
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
      1. Datapath optimization
      2. Hardware-software codesign
    2. Logic synthesis
      1. Circuit optimization
  2. Integrated circuits
    1. Semiconductor memory

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Multiple-block ahead branch predictors
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A basic rule in computer architecture is that a processor cannot execute an application faster than it fetches its instructions. This paper presents a novel cost-effective mechanism called the two-block ahead branch predictor. Information from the ...
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A basic rule in computer architecture is that a processor cannot execute an application faster than it fetches its instructions. This paper presents a novel cost-effective mechanism called the two-block ahead branch predictor. Information from the ...
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Accurate branch prediction and instruction fetch prediction of a microprocessor are critical to achieve high performance. For a processor which fetches and executes multiple instructions per cycle, an accurate and high bandwidth instruction fetching ...

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Information & Contributors

Information

Published In

cover image ACM SIGOPS Operating Systems Review

ACM SIGOPS Operating Systems Review Volume 30, Issue 5

Dec. 1996

273 pages

ISSN:0163-5980

DOI:10.1145/248208

Chairmen:
Bill Dally
Massachusetts Institute of Technology
,
Susan Eggers
Univ. of Washington, Seattle

Issue’s Table of Contents

ASPLOS VII: Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
October 1996
290 pages
ISBN:0897917677
DOI:10.1145/237090
Chairmen:
Bill Dally
Massachusetts Institute of Technology
,
Susan Eggets
Univ. of Washington, Seattle

Copyright © 1996 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 September 1996

Published in SIGOPS Volume 30, Issue 5

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Cited By

Tran KCarlson TKoukos KSjalander MSpiliopoulos VKaxiras SJimborean A(2018)Static Instruction Scheduling for High Performance on Limited HardwareIEEE Transactions on Computers10.1109/TC.2017.276964167:4(513-527)Online publication date: 1-Apr-2018
https://doi.org/10.1109/TC.2017.2769641
Tran KCarlson TKoukos KSjälander MSpiliopoulos VKaxiras SJimborean AReddi VSmith ATang L(2017)Clairvoyance: look-ahead compile-time schedulingProceedings of the 2017 International Symposium on Code Generation and Optimization10.5555/3049832.3049852(171-184)Online publication date: 4-Feb-2017
https://dl.acm.org/doi/10.5555/3049832.3049852
Tran KCarlson TKoukos KSjalander MSpiliopoulos VKaxiras SJimborean A(2017)Clairvoyance: Look-ahead compile-time scheduling2017 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)10.1109/CGO.2017.7863738(171-184)Online publication date: Feb-2017
https://doi.org/10.1109/CGO.2017.7863738
Goossens B(2001)Handling 16 instructions per cycle in a superscalar processorFuture Generation Computer Systems10.1016/S0167-739X(00)00053-417:6(699-709)Online publication date: 1-Apr-2001
https://dl.acm.org/doi/10.1016/S0167-739X%2800%2900053-4
Mohammadi MHan SAtoofian EBaniasadi AAamodt TDally W(2020)Energy Efficient On-Demand Dynamic Branch Prediction ModelsIEEE Transactions on Computers10.1109/TC.2019.295671069:3(453-465)Online publication date: 1-Mar-2020
https://doi.org/10.1109/TC.2019.2956710
Park JEun CCho HJeong O(2019)A Branch Predictor Design to Improve Prediction Rate by Reducing Index Aliasing in Application Processors2019 12th International Conference on Information & Communication Technology and System (ICTS)10.1109/ICTS.2019.8850959(193-196)Online publication date: Jul-2019
https://doi.org/10.1109/ICTS.2019.8850959
Mittal S(2018)A survey of techniques for dynamic branch predictionConcurrency and Computation: Practice and Experience10.1002/cpe.466631:1Online publication date: 2-Sep-2018
https://doi.org/10.1002/cpe.4666
Mohammadi MHan SAamodt TDally W(2015)On-Demand Dynamic Branch PredictionIEEE Computer Architecture Letters10.1109/LCA.2014.233082014:1(50-53)Online publication date: 1-Jan-2015
https://doi.org/10.1109/LCA.2014.2330820
Choudhary NDwiel BRotenberg E(2012)A physical design study of fabscalar-generated superscalar cores2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)10.1109/VLSI-SoC.2012.7332095(165-170)Online publication date: Oct-2012
https://doi.org/10.1109/VLSI-SoC.2012.7332095
Choudhary NDwiel BRotenberg E(2012)A physical design study of fabscalar-generated superscalar cores2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)10.1109/VLSI-SoC.2012.6379024(165-170)Online publication date: Oct-2012
https://doi.org/10.1109/VLSI-SoC.2012.6379024
Show More Cited By

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