Parallel automated wire-routing with a number of competing processors
Pages 310 - 317
Abstract
The purpose of the automated wire routing for VLSI and printed circuit board design is to connect a number of terminal pairs distributed throughout wiring plane with net paths which do not intersect each other. Although maze running and line search are well known algorithms used for this purpose, they need a considerable computing time. To reduce it we have developed a new parallel routing algorithm in which a number of processors compete in wiring different nets independent of each other, and one master processor verifies their results and judges. The master processor also delivers an assignment message to the processors. The efficiency of this algorithm was evaluated on a binary-tree multicomputer and more than 50 times of speedup was obtained when 3000 random nets were routed by using 63 processing elements.
References
[1]
Suzuki,Y.,Matsunaga, Y.,Tachibana, M, Ohtsuki,T.: A Hardware Maze Router with Application to Interactive Rip-up and Reroute, lEEE Trans. on CAD, VoI. CAD-5, No. 4, pp. 466-476 (0ct. 1988)
[2]
Watanabe, T.,Sugiyama, Y.: A New Routing Algorithm and its Hardware Implementation, Proc. 23rd Design Automation Conf.,pp. 574-580 (1986)
[3]
Takahashi, Y,Suzue, T.,Kashimoto. S.: Parallel Mazerunning and Line Search Algorithms for LSI CAD on Binary-Tree Multiprocessor, Proc. World Conference on lnformation/Communication, Seoul, June 1989, pp. 128-136.
[4]
Ohtsuki, T: Layout Design and Verification, North- Holland, Amsterdam, Chapter 3.(1986)
[5]
Endo, T.,Matuo, g.,Shirakata, S.,Tsutitani,H.,Takahashi,Y: System Architecture and Performance Evaluation of Binary-Tree Machine Coral 68K, Technical Report of IPSJ, VoI. 87, No. 45,87-CA-66-5 (1987)(in Japanese)
[6]
Takahashi, Y.,Endo, T.,Matsuo, K.,Tsuchitani, H.: Development and Performance Evaluation of the Coral 68K Binary-Tree Parallel Computer, Trans. IPSJ, Vol. 30, No.l, pp. 46-57 (1989) (in Japanese)
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- Parallel automated wire-routing with a number of competing processors
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Parallel automated wire-routing with a number of competing processors
ICS '90: Proceedings of the 4th international conference on SupercomputingThe purpose of the automated wire routing for VLSI and printed circuit board design is to connect a number of terminal pairs distributed throughout wiring plane with net paths which do not intersect each other. Although maze running and line search are ...
Hierarchical Wire Routing
We propose a new approach to automatic wire routing of VLSI chips which is applicable to interconnection problem in uniform structures such as gate arrays, switchboxes, channels. Popularity of gate arrays technologies still remains high among VLSI chip ...
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Published In
Sept. 1990
489 pages
Copyright © 1990 ACM.
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Association for Computing Machinery
New York, NY, United States
Publication History
Published: 01 June 1990
Published in SIGARCH Volume 18, Issue 3b
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