research-article

Mixed-size concurrency: ARM, POWER, C/C++11, and SC

Authors:

Christopher Pulte,

Kyndylan Nienhuis,

Kathryn E. Gray,

Peter SewellAuthors Info & Claims

ACM SIGPLAN Notices, Volume 52, Issue 1

Pages 429 - 442

https://doi.org/10.1145/3093333.3009839

Published: 01 January 2017 Publication History

Abstract

Previous work on the semantics of relaxed shared-memory concurrency has only considered the case in which each load reads the data of exactly one store. In practice, however, multiprocessors support mixed-size accesses, and these are used by systems software and (to some degree) exposed at the C/C++ language level. A semantic foundation for software, therefore, has to address them.

We investigate the mixed-size behaviour of ARMv8 and IBM POWER architectures and implementations: by experiment, by developing semantic models, by testing the correspondence between these, and by discussion with ARM and IBM staff. This turns out to be surprisingly subtle, and on the way we have to revisit the fundamental concepts of coherence and sequential consistency, which change in this setting. In particular, we show that adding a memory barrier between each instruction does not restore sequential consistency. We go on to extend the C/C++11 model to support non-atomic mixed-size memory accesses.

This is a necessary step towards semantics for real-world shared-memory concurrent code, beyond litmus tests.

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Index Terms

Mixed-size concurrency: ARM, POWER, C/C++11, and SC

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Published In

cover image ACM SIGPLAN Notices

ACM SIGPLAN Notices Volume 52, Issue 1

POPL '17

January 2017

901 pages

ISSN:0362-1340

EISSN:1558-1160

DOI:10.1145/3093333

Editor:
Matthew Fluet

Issue’s Table of Contents

POPL '17: Proceedings of the 44th ACM SIGPLAN Symposium on Principles of Programming Languages
January 2017
901 pages
ISBN:9781450346603
DOI:10.1145/3009837
General Chair:
Giuseppe Castagna
Paris Diderot University, France / CNRS, France
,
Program Chair:
Andrew D. Gordon
Microsoft Research, UK / University of Edinburgh, UK

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Published: 01 January 2017

Published in SIGPLAN Volume 52, Issue 1

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https://dl.acm.org/doi/10.1145/3428294
Watt CRossberg APichon-Pharabod J(2019)Weakening WebAssemblyProceedings of the ACM on Programming Languages10.1145/33605593:OOPSLA(1-28)Online publication date: 10-Oct-2019
https://dl.acm.org/doi/10.1145/3360559
Marmanis IKokologiannakis MVafeiadis V(2025)Model Checking C/C++ with Mixed-Size AccessesProceedings of the ACM on Programming Languages10.1145/37049119:POPL(2232-2252)Online publication date: 9-Jan-2025
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Hammond ALiu ZPérami TSewell PBirkedal LPichon-Pharabod J(2024)An Axiomatic Basis for Computer Programming on the Relaxed Arm-A Architecture: The AxSL LogicProceedings of the ACM on Programming Languages10.1145/36328638:POPL(604-637)Online publication date: 5-Jan-2024
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Sato SMizuhashi TKimura GTaura K(2024)Efficiently Adapting Stateless Model Checking for C11/C++11 to Mixed-Size AccessesProgramming Languages and Systems10.1007/978-981-97-8943-6_17(346-364)Online publication date: 23-Oct-2024
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Kokologiannakis MLahav OVafeiadis V(2023)Kater: Automating Weak Memory Model Metatheory and Consistency CheckingProceedings of the ACM on Programming Languages10.1145/35712127:POPLOnline publication date: 11-Jan-2023
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