research-article

An Efficient Self-Routing and Non-Blocking Interconnection Network on Chip

Authors:

Klaus Schneider,

Ankesh JainAuthors Info & Claims

NoCArc '17: Proceedings of the 10th International Workshop on Network on Chip Architectures

Article No.: 4, Pages 1 - 6

https://doi.org/10.1145/3139540.3139546

Published: 14 October 2017 Publication History

Abstract

In this paper, we present a new self-routing and non-blocking uni-cast interconnection network based on binary radix sorting that is more efficient than comparable other interconnection networks. To substantiate this claim, we first derive the asymptotic complexities of the size and depth of our network's circuit netlist. Moreover, we have implemented our network as well as other related radix-based sorting networks using 65nm CMOS chip technology. We compare the maximal frequency, the required chip area, and the power consumption of these circuits. Our evaluation shows that our network is best among the considered radix-based networks regardless whether the maximal frequency, the chip area or the power consumption is considered.

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Cited By

Froemmer JBannow NAue AGrimm CSchneider K(2019)Flexible Data Flow Architecture for Embedded Hardware AcceleratorsAlgorithms and Architectures for Parallel Processing10.1007/978-3-030-38991-8_3(33-47)Online publication date: 9-Dec-2019
https://dl.acm.org/doi/10.1007/978-3-030-38991-8_3
Jain TSchneider KHu KZhan N(2018)Optimal self-routing split modules for radix-based interconnection networksProceedings of the 16th ACM-IEEE International Conference on Formal Methods and Models for System Design10.5555/3343872.3343884(99-108)Online publication date: 15-Oct-2018
https://dl.acm.org/doi/10.5555/3343872.3343884
Jain TSchneider K(2018)Routing Partial Permutations in Interconnection Networks based on Radix Sorting2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)10.1109/ReCoSoC.2018.8449372(1-10)Online publication date: Jul-2018
https://doi.org/10.1109/ReCoSoC.2018.8449372
Show More Cited By

Index Terms

An Efficient Self-Routing and Non-Blocking Interconnection Network on Chip
1. Computer systems organization
  1. Architectures
    1. Distributed architectures
    2. Parallel architectures
      1. Interconnection architectures
  2. Embedded and cyber-physical systems
2. Networks
  1. Network types
    1. Network on chip

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cover image ACM Conferences

NoCArc '17: Proceedings of the 10th International Workshop on Network on Chip Architectures

October 2017

63 pages

ISBN:9781450355421

DOI:10.1145/3139540

Copyright © 2017 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 14 October 2017

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MICRO-50

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SIGMICRO

MICRO-50: The 50th Annual IEEE/ACM International Symposium on Microarchitecture

October 14, 2017

MA, Cambridge, USA

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NoCArc '17 Paper Acceptance Rate 6 of 20 submissions, 30%;

Overall Acceptance Rate 46 of 122 submissions, 38%

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Cited By

Froemmer JBannow NAue AGrimm CSchneider K(2019)Flexible Data Flow Architecture for Embedded Hardware AcceleratorsAlgorithms and Architectures for Parallel Processing10.1007/978-3-030-38991-8_3(33-47)Online publication date: 9-Dec-2019
https://dl.acm.org/doi/10.1007/978-3-030-38991-8_3
Jain TSchneider KHu KZhan N(2018)Optimal self-routing split modules for radix-based interconnection networksProceedings of the 16th ACM-IEEE International Conference on Formal Methods and Models for System Design10.5555/3343872.3343884(99-108)Online publication date: 15-Oct-2018
https://dl.acm.org/doi/10.5555/3343872.3343884
Jain TSchneider K(2018)Routing Partial Permutations in Interconnection Networks based on Radix Sorting2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)10.1109/ReCoSoC.2018.8449372(1-10)Online publication date: Jul-2018
https://doi.org/10.1109/ReCoSoC.2018.8449372
Jain TSchneider K(2018)Optimal Self-Routing Split Modules for Radix-based Interconnection Networks2018 16th ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)10.1109/MEMCOD.2018.8556886(1-10)Online publication date: Oct-2018
https://doi.org/10.1109/MEMCOD.2018.8556886
Jain TSchneider KJain A(2017)Deriving concentrators from binary sorters using half cleaners2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)10.1109/RECONFIG.2017.8279784(1-6)Online publication date: Dec-2017
https://doi.org/10.1109/RECONFIG.2017.8279784

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