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Systematic hardware adaptation of systolic algorithms

Authors:

M. Valero-Garcia,

J. M. Llaberia,

M. ValeroAuthors Info & Claims

ISCA '89: Proceedings of the 16th annual international symposium on Computer architecture

Pages 96 - 104

https://doi.org/10.1145/74925.74937

Published: 01 April 1989 Publication History

Abstract

In this paper we propose a methodology to adapt Systolic Algorithms to the hardware selected for their implementation. Systolic Algorithms obtained can be efficiently implemented using Pipelined Functional Units. The methodology is based on two transformation rules. These rules are applied to an initial Systolic Algorithm, possibly obtained through one of the design methodologies proposed by other authors. Parameters for these transformations are obtained from the specification of the hardware to be used. The methodology has been particularized in the case of one-dimensional Systolic Algorithms with data contraflow.

References

[1]

H.T. Kung and C.E. Leiserson. "Systolic Arrays (for VLSI), Sparse Matrix Proc. 1978 1979, Society for Industrial and Applied Mathematics (SIAM), pp. 256-282. (A slightly dserent version appears in the text Introduction to VLSI Systems, Section 8.3. C.A. Mead and L.A. Conway, eds.,1980, Addison-Wesley, Reading, Mass.).

[2]

H.T. Kung, "Why Systolic Architectures?," Computer, Vol. 15, No. 1. Jan. 1982, pp. 37-46.

Digital Library

[3]

C.E. Leiserson and J.B. Saxe. "Optimizing Synchronous Systems," Proc. 22nd Annual Symp. on Foundations of Computer Science, Oct. 1961, pp. 23-36.

[4]

S.Y. Kung, "On Supercom Array Processors," Proc. IE Ep uting with SystolicWavefront E Vol. 72, No. 7. July 1984.

[5]

D.I. Moldovan, "On the Design of Algorithms for VLSI Systolic Arrays,""Proc. IEEE,Vol. 71, No. 1, pp. 113-120,1983.

[6]

P. Quinton, "Automatic Synthesis of Systolic Arrays form Unifor,m Recurrent Equations" 11 th Int'l Symp computer Architecture, pp. 208-214, IEEE & ACM, June 1984.

Digital Library

[7]

G.J. Li, B.W. Wah, "The Design of Optimal Systotic Arrays," IEEE.Trans. on Computers, Vol. C-34, No. 10, Jan. 1985, pp.

[8]

M. Chen, "Synthesizing VLSI Architectures: Dynamic Programming Solver," Int' 1 Conf. on Parallel Processing, 1986, pp. 776-784.

[9]

I.V. Ramakrishnan and D.S. Fussell, "On Mapping Homo eneous Graphs on a Linear Array-Processor Model," Int'l %nf Parallel Processing 1983 pp. 440-447.

[10]

J.A.B. Fortes, K.S. Fuand B.W. Wah, "S stematic Approaches to the Desi ity Proc. Znt'l CF of Algorithmically Spec led Systolic Arrays," onf Acoustic, Speech and Signal Processing, 1985, pp. 8.9.1-8.9.5.

[11]

J.A.3. Fortes, K.S. Fu and B.W. Wah. "Systematic Design Approaches to Algorithmically Specified Systolic Arrays,' Computer Architecture Concepts and Systems, North Holland 1988, pp. 455-494.

Digital Library

[12]

D. Heller, "Partitionin Big Matrices for Small Systolic Arays" Chapter 11 of VLSI and Modern Signal Processing, S.Y. Kung, H.J. Whitehouse and T. Kailath eds. 1985, Prentice-Hall, Englewood Cliffs, N.J., pp. 185-199.

[13]

R. Schreiber and P.J. Kucks, "Systolic Linear Algebra Machines in Digital Signal Processing," Chapiter 22 of VLSI and Modern Signal Processing, S.Y. Kung, H.J. Whitehouse and T. Kailath eds. 1985, Prentice-Hall, Englewood Cliffs, N.J., pp.389-405.

[14]

J.J. Navarro, J.M. LLaberia and M. Valero, "Partitioning: An Essential Ste in Mapping Algorithms Into Systolic Array Processors, 4 omputer, Vol. 20, No. 7, July 1987, pp. 77-89.

Digital Library

[15]

D.I. Moldovan and J.A.B. Fortes, "Partitioning and Mapping Algorithms Into Fixed Size Systolic Arrays," IEEE Trans. on Computers, Vol. C-35, No. 1, Jan. 1986, pp. l-12.

Digital Library

[16]

H.W. Neils and E.F. Deprettere, "Automatic Desi n and Partitioning of SystolicWavefront Arrays for VLSI," (?ircuits Systems SignalProcess, Vol. 7, No. 2,1988, pp. 235-252.

[17]

H. Moreno and T. Lan "Graph-based Partitionin of Matrix Algorithms for Systo lc Arrays: Application to % ransitive Closure," 1988 Int l Conf. on Parallel Processing.

[18]

H.T. Kung, L.M. Ruane and D.W.L. Yen, "Two-Level Pipelined S stolic Array for Multidimensional Convolution," Image and kJ. won Computing, Vol. 1, No. 1, Febr. 1983 pp. 30-36

[19]

D.W.L. Yen and A.V. Kulkarni, "Systolic Processing and an Implementation for Signal and Image Processing," IEEE Trans. on Computers. Vol. C-31, No. 10, Oct. 1982, pp. lOOO- 1009.

[20]

H.T. Kung and M.S. Lam, "Wafer-Scale Integration and Two- Level Pipelined Implementation of Systolic Arrays," Journal of Parallel and Distributed Processing, Vol. 1, No, 1,1984.

[21]

M. Valero-Garcia, J.J. Navarro, J.M. LLaberia and M. Valero, "Systematic Desi of Two-Level Pipelined Systolic Arrays with Data Contra flow," Proc. IEEE lnt'l Conf. on Circuits and Systems 1988. DD. 2521-2525.

[22]

H.T. Kung and W.T. Lin, "An Algebra for Systolic Comoutation." Elliotic Problem Solvers II. Academic Press 1984; pp. 32-63.

[23]

C.E. Leiserson, "Area-Efficient VLSI Computations," PhD dissertation, Departament of Computer Science, Carnegie- Mellon University, Oct. 1981, Published in book form as part of the ACM Doctoral Dissertation Award Series by the MIT Press, Cambridge, Massachusetts, 1983.

Digital Library

[24]

N. Torralba and J.J. Navarrq, A One-Dimensional Systolic Arrays for Solving Arbitrarily Large Least Mean Square Prob ems, ""Proc. Int'l Conf. on Systolic Arrays. May 1988 pp. 103-112.

[25]

J.J. Navarro, J.M. LLaberia and M. Valero, ""Computing Size- Independent Matrix Problems on Systolic Array Processors," 13th Int'l Symp. Computer Architecture, 1986, pp. 271-279

Digital Library

[26]

J.J. Navarrq, J.M. LLeberia and M. Valero, "Solving Matrix Problems,wwlth No Size Restriction, on a Systolic Array g;r. Int 1 Conf. Parallel Processtng, Aug. 1986, pp. 676-

[27]

M. Valero-Garcia, J.M. Llaberia and J.J. Navarro, "Considering Implementation Features in the Design of Systolic Array Processors," Internal Report, RR 88/01, Facultad de Informatica Barcelona, Spain.

[28]

Floating Point Division/ Square Rootl IEEE Arithmetic WTL 1032/1033, Application Note, Weitek, 1983.

[29]

C.V. Ramamoorthy, "Pipeline Architecture," Computing Surveys, Vol. 9, No. 1, March 1977, pp 61-102.

Digital Library

[30]

P.M. Kogge, "The Architecture ef Pipelined Computers," Hemisphere Publishing Corporation, 1981.

Cited By

Suarez ALlaberia JFernandez A(1992)Scheduling partitions in systolic algorithms[1992] Proceedings of the International Conference on Application Specific Array Processors10.1109/ASAP.1992.218540(619-633)Online publication date: 1992
https://doi.org/10.1109/ASAP.1992.218540
Valero-Garcia MNavarro JLlaberia JValero M(1990)Implementation of systolic algorithms using pipelined functional units[1990] Proceedings of the International Conference on Application Specific Array Processors10.1109/ASAP.1990.145464(272-283)Online publication date: 1990
https://doi.org/10.1109/ASAP.1990.145464
Van Dongen V(2005)Mapping uniform recurrences onto small size arraysPARLE '91 Parallel Architectures and Languages Europe10.1007/BFb0035105(191-208)Online publication date: 23-Jun-2005
https://doi.org/10.1007/BFb0035105
Show More Cited By

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Systematic hardware adaptation of systolic algorithms

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Published In

cover image ACM Conferences

ISCA '89: Proceedings of the 16th annual international symposium on Computer architecture

April 1989

426 pages

ISBN:0897913191

DOI:10.1145/74925

Chairman:
Jean-Claude Syre

ACM SIGARCH Computer Architecture News Volume 17, Issue 3
Special Issue: Proceedings of the 16th annual international symposium on Computer Architecture
June 1989
400 pages
ISSN:0163-5964
DOI:10.1145/74926
Editor:
Jean-Claude Syre
Issue’s Table of Contents

Copyright © 1989 Authors.

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SIGARCH: ACM Special Interest Group on Computer Architecture
IEEE-CS: Computer Society

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 April 1989

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Cited By

Suarez ALlaberia JFernandez A(1992)Scheduling partitions in systolic algorithms[1992] Proceedings of the International Conference on Application Specific Array Processors10.1109/ASAP.1992.218540(619-633)Online publication date: 1992
https://doi.org/10.1109/ASAP.1992.218540
Valero-Garcia MNavarro JLlaberia JValero M(1990)Implementation of systolic algorithms using pipelined functional units[1990] Proceedings of the International Conference on Application Specific Array Processors10.1109/ASAP.1990.145464(272-283)Online publication date: 1990
https://doi.org/10.1109/ASAP.1990.145464
Van Dongen V(2005)Mapping uniform recurrences onto small size arraysPARLE '91 Parallel Architectures and Languages Europe10.1007/BFb0035105(191-208)Online publication date: 23-Jun-2005
https://doi.org/10.1007/BFb0035105
Yáñez ABarro SBugarin A(1991)Backpropagation multilayer perceptron: A modular implementationArtificial Neural Networks10.1007/BFb0035905(285-295)Online publication date: 1991
https://doi.org/10.1007/BFb0035905

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