article

Unbounded page-based transactional memory

Authors:

Satish Narayanasamy,

Ganesh Venkatesh,

Michael Van Biesbrouck,

Osvaldo ColavinAuthors Info & Claims

ACM SIGOPS Operating Systems Review, Volume 40, Issue 5

Pages 347 - 358

https://doi.org/10.1145/1168917.1168901

Published: 20 October 2006 Publication History

Abstract

Exploiting thread level parallelism is paramount in the multicore era. Transactions enable programmers to expose such parallelism by greatly simplifying the multi-threaded programming model. Virtualized transactions (unbounded in space and time) are desirable, as they can increase the scope of transactions' use, and thereby further simplify a programmer's job. However, hardware support is essential to support efficient execution of unbounded transactions. In this paper, we introduce Page-based Transactional Memory to support unbounded transactions. We combine transaction bookkeeping with the virtual memory system to support fast transaction conflict detection, commit, abort, and to maintain transactions' speculative data.

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Cited By

WANG SWU DPANG ZYANG X(2009)HybridTCache: Tightly Coupled Hybrid Transactional Memory System to Support Efficient Unbounded Transactions with Strong IsolationChinese Journal of Computers10.3724/SP.J.1016.2008.0190731:11(1907-1917)Online publication date: 16-Oct-2009
https://doi.org/10.3724/SP.J.1016.2008.01907
Jain AKadiyala DDaglis A(2023)Safety Hints for HTM Capacity Abort Mitigation2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071113(206-219)Online publication date: Feb-2023
https://doi.org/10.1109/HPCA56546.2023.10071113
Sustran ZProtic J(2021)Migration in Hardware Transactional Memory on Asymmetric MultiprocessorIEEE Access10.1109/ACCESS.2021.30775399(69346-69364)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3077539
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Index Terms

Unbounded page-based transactional memory
1. Computer systems organization
  1. Architectures
    1. Parallel architectures

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Unbounded page-based transactional memory
Proceedings of the 2006 ASPLOS Conference

Exploiting thread level parallelism is paramount in the multicore era. Transactions enable programmers to expose such parallelism by greatly simplifying the multi-threaded programming model. Virtualized transactions (unbounded in space and time) are ...
Unbounded page-based transactional memory
Proceedings of the 2006 ASPLOS Conference

Exploiting thread level parallelism is paramount in the multicore era. Transactions enable programmers to expose such parallelism by greatly simplifying the multi-threaded programming model. Virtualized transactions (unbounded in space and time) are ...
Unbounded page-based transactional memory
ASPLOS XII: Proceedings of the 12th international conference on Architectural support for programming languages and operating systems

Exploiting thread level parallelism is paramount in the multicore era. Transactions enable programmers to expose such parallelism by greatly simplifying the multi-threaded programming model. Virtualized transactions (unbounded in space and time) are ...

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Published In

cover image ACM SIGOPS Operating Systems Review

ACM SIGOPS Operating Systems Review Volume 40, Issue 5

Proceedings of the 2006 ASPLOS Conference

December 2006

425 pages

ISSN:0163-5980

DOI:10.1145/1168917

Issue’s Table of Contents

ASPLOS XII: Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
October 2006
440 pages
ISBN:1595934510
DOI:10.1145/1168857
General Chair:
John Paul Shen
Intel Corp.
,
Program Chair:
Margaret R. Martonosi
Princeton University

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 20 October 2006

Published in SIGOPS Volume 40, Issue 5

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Cited By

WANG SWU DPANG ZYANG X(2009)HybridTCache: Tightly Coupled Hybrid Transactional Memory System to Support Efficient Unbounded Transactions with Strong IsolationChinese Journal of Computers10.3724/SP.J.1016.2008.0190731:11(1907-1917)Online publication date: 16-Oct-2009
https://doi.org/10.3724/SP.J.1016.2008.01907
Jain AKadiyala DDaglis A(2023)Safety Hints for HTM Capacity Abort Mitigation2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071113(206-219)Online publication date: Feb-2023
https://doi.org/10.1109/HPCA56546.2023.10071113
Sustran ZProtic J(2021)Migration in Hardware Transactional Memory on Asymmetric MultiprocessorIEEE Access10.1109/ACCESS.2021.30775399(69346-69364)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3077539
Majid ADonne CMaeng KColin AYildirim KLucia BPawełczak P(2020)Dynamic Task-based Intermittent Execution for Energy-harvesting DevicesACM Transactions on Sensor Networks10.1145/336028516:1(1-24)Online publication date: 4-Feb-2020
https://dl.acm.org/doi/10.1145/3360285
Wang ZKozuch MMowry TSeshadri V(2019)Multiversioned Page Overlays: Enabling Faster Serializable Hardware Transactional MemoryProceedings of the International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT.2019.00038(394-407)Online publication date: 23-Sep-2019
https://dl.acm.org/doi/10.1109/PACT.2019.00038
Subramanian SJeffrey MAbeydeera MLee HYing VEmer JSanchez D(2017)FractalACM SIGARCH Computer Architecture News10.1145/3140659.308021845:2(587-599)Online publication date: 24-Jun-2017
https://dl.acm.org/doi/10.1145/3140659.3080218
Tanasic IGelado IJorda MAyguade ENavarro NHunter HMoreno JEmer JSanchez D(2017)Efficient exception handling support for GPUsProceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3123939.3123950(109-122)Online publication date: 14-Oct-2017
https://dl.acm.org/doi/10.1145/3123939.3123950
Subramanian SJeffrey MAbeydeera MLee HYing VEmer JSanchez D(2017)FractalProceedings of the 44th Annual International Symposium on Computer Architecture10.1145/3079856.3080218(587-599)Online publication date: 24-Jun-2017
https://dl.acm.org/doi/10.1145/3079856.3080218
Litz HBraun BCheriton DZaks AMendelson BRauchwerger LHwu W(2016)EXCITE-VMProceedings of the 2016 International Conference on Parallel Architectures and Compilation10.1145/2967938.2967955(401-412)Online publication date: 11-Sep-2016
https://dl.acm.org/doi/10.1145/2967938.2967955
Titos-Gil JAcacio M(2015)Hardware Approaches to Transactional Memory in Chip MultiprocessorsHandbook on Data Centers10.1007/978-1-4939-2092-1_27(805-835)Online publication date: 17-Mar-2015
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