research-article

A design approach to automatically generate on-chip monitors during high-level synthesis of hardware accelerator

Authors:

Mohamed Ben Hammouda,

Philippe Coussy,

Loic LagadecAuthors Info & Claims

GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSI

Pages 273 - 278

https://doi.org/10.1145/2591513.2591521

Published: 20 May 2014 Publication History

Abstract

Embedded systems often implement safety critical applications making security a more and more important aspect in their design. Control-Flow Integrity (CFI) attacks are used to modify program behavior and can lead to learn valuable information directly or indirectly by perturbing a system and creating failures. Although CFI attacks are well-known in computer systems, they have been recently shown to be practical and feasible on embedded systems as well. In this context, CFI checks are mainly used to detect unintended software behaviors while very few works address non programmable hardware component monitoring. In this paper, we present a hardware-assisted paradigm to enhance embedded system security by detecting and preventing unintended hardware behavior. We propose a design approach that designs on-chip monitors (OCM) during High-Level Synthesis (HLS) of hardware accelerators (HWacc). Synthesis of OCM is introduced as a set of steps realized concurrently to the HLS flow of HWacc. Automatically generated OCM checks at runtime both the input/output timing behavior and the control flow of the monitored HWacc. Experimental results show the interest of the proposed approach: the error coverage on the control flow ranges from 99.75% to 100% while in average the OCM area overhead is less than 10%, the clock period overhead is at worst less than 5% and impact on the synthesis time is negligible.

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Cited By

Veeranna NSchafer B(2017)Hardware Trojan Detection in Behavioral Intellectual Properties (IP's) Using Property Checking TechniquesIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2016.25850465:4(576-585)Online publication date: 1-Oct-2017
https://doi.org/10.1109/TETC.2016.2585046
Hammouda MCoussy PLagadec L(2017)A Unified Design Flow to Automatically Generate On-Chip Monitors During High-Level Synthesis of Hardware AcceleratorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.258727836:3(384-397)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2587278
Pinilla JWilton S(2016)Enhanced source-level instrumentation for FPGA in-system debug of High-Level Synthesis designs2016 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2016.7929514(109-116)Online publication date: Dec-2016
https://doi.org/10.1109/FPT.2016.7929514

Index Terms

A design approach to automatically generate on-chip monitors during high-level synthesis of hardware accelerator
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
  2. Hardware test

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cover image ACM Conferences

GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSI

May 2014

376 pages

ISBN:9781450328166

DOI:10.1145/2591513

General Chairs:
Joseph R. Cavallaro
Rice University, USA
,
Tong Zhang
Rensselaer Polytechnic Inst., USA
,
Program Chairs:
Alex K. Jones
University of Pittsburgh, USA
,
Hai (Helen) Li
University of Pittsburgh, USA

Copyright © 2014 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

Publication History

Published: 20 May 2014

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GLSVLSI '14

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GLSVLSI '14: Great Lakes Symposium on VLSI 2014

May 21 - 23, 2014

Texas, Houston, USA

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GLSVLSI '14 Paper Acceptance Rate 49 of 179 submissions, 27%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Veeranna NSchafer B(2017)Hardware Trojan Detection in Behavioral Intellectual Properties (IP's) Using Property Checking TechniquesIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2016.25850465:4(576-585)Online publication date: 1-Oct-2017
https://doi.org/10.1109/TETC.2016.2585046
Hammouda MCoussy PLagadec L(2017)A Unified Design Flow to Automatically Generate On-Chip Monitors During High-Level Synthesis of Hardware AcceleratorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.258727836:3(384-397)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2587278
Pinilla JWilton S(2016)Enhanced source-level instrumentation for FPGA in-system debug of High-Level Synthesis designs2016 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2016.7929514(109-116)Online publication date: Dec-2016
https://doi.org/10.1109/FPT.2016.7929514

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