research-article

Dynamic associativity management using utility based way-sharing

Authors:

Shirshendu Das,

Hemangee K. KapoorAuthors Info & Claims

SAC '15: Proceedings of the 30th Annual ACM Symposium on Applied Computing

Pages 1919 - 1924

https://doi.org/10.1145/2695664.2695783

Published: 13 April 2015 Publication History

Abstract

The non-uniform distribution of memory accesses of todays applications affect the performance of cache memories. Due to such non-uniform accesses some sets of large sized caches are used heavily while some other sets are used lightly. This paper presents a technique WS-DAM, to dynamically increase the associativity of the heavily used sets without increasing the cache size. The heavily used sets can use the idle ways of the lightly used sets to distribute the load. A limited number of ways from every lightly used set are reserved for the heavily used sets. To search a block in a heavily used set, both: the set and the entire reserve area is searched. To reduce the cost of searching the entire reserve storage an additional tag-array is used. During execution the sets are re-categorized at intervals. The proposed technique needs much lesser storage, area and power overhead as compared to the other similar techniques. It improves both miss rate and CPI by 14.46% and 6.63% respectively as compared to an existing technique called V-Way. WS-DAM is also compared with another existing proposal called CMP-VR and it improves the performance by 9% and 4.20% in terms of miss-rate and CPI respectively.

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Cited By

Saha SChakraborty SZhai XEhsan SMcDonald-Maier K(2022)ACCURATE: Accuracy Maximization for Real-Time Multicore Systems With Energy-Efficient Way-Sharing CachesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.316140741:12(5246-5260)Online publication date: Dec-2022
https://doi.org/10.1109/TCAD.2022.3161407
Shatnawi AAlsaedeen M(2018)Reducing the second-level cache conflict misses using a set folding techniqueThe Journal of Supercomputing10.1007/s11227-017-2174-874:2(970-993)Online publication date: 1-Feb-2018
https://dl.acm.org/doi/10.1007/s11227-017-2174-8
Chakraborty SDas SKapoor H(2015)Power aware cache miss reduction by energy efficient victim retention2015 19th International Symposium on VLSI Design and Test10.1109/ISVDAT.2015.7208078(1-6)Online publication date: Jun-2015
https://doi.org/10.1109/ISVDAT.2015.7208078

Index Terms

Dynamic associativity management using utility based way-sharing
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Interconnection architectures

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cover image ACM Conferences

SAC '15: Proceedings of the 30th Annual ACM Symposium on Applied Computing

April 2015

2418 pages

ISBN:9781450331968

DOI:10.1145/2695664

Conference Chairs:
Roger L. Wainwright
University of Tulsa
,
Juan Manuel Corchado
University of Salamanca, Spain
,
Program Chairs:
Alessio Bechini
University of Pisa, Italy
,
Jiman Hong
Soongsil University, South Korea

Copyright © 2015 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 13 April 2015

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SAC 2015: Symposium on Applied Computing

April 13 - 17, 2015

Salamanca, Spain

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SAC '15 Paper Acceptance Rate 291 of 1,211 submissions, 24%;

Overall Acceptance Rate 1,650 of 6,669 submissions, 25%

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Cited By

Saha SChakraborty SZhai XEhsan SMcDonald-Maier K(2022)ACCURATE: Accuracy Maximization for Real-Time Multicore Systems With Energy-Efficient Way-Sharing CachesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.316140741:12(5246-5260)Online publication date: Dec-2022
https://doi.org/10.1109/TCAD.2022.3161407
Shatnawi AAlsaedeen M(2018)Reducing the second-level cache conflict misses using a set folding techniqueThe Journal of Supercomputing10.1007/s11227-017-2174-874:2(970-993)Online publication date: 1-Feb-2018
https://dl.acm.org/doi/10.1007/s11227-017-2174-8
Chakraborty SDas SKapoor H(2015)Power aware cache miss reduction by energy efficient victim retention2015 19th International Symposium on VLSI Design and Test10.1109/ISVDAT.2015.7208078(1-6)Online publication date: Jun-2015
https://doi.org/10.1109/ISVDAT.2015.7208078

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