Region-Based Data Layout via Data Reuse Analysis
Pages 49 - 59
Abstract
Data-structure splicing techniques, such as structure splitting, field reordering, and pointer inlining reorganize data structures to improve cache and translation look-aside buffer (TLB) utilization. Structure types are typically transformed globally in the program, requiring updates to all references to elements of a transformed type. These techniques often rely on instrumentation, tracing, or sampling to create models that guide their transformations. Furthermore, compilers often cannot prove that their transformations are legal and must rely on manual inspection and manual transformation. Applying data-layout transformations locally -- as opposed to globally -- to regions of code removes the need for expensive profiling and simplifies legality verification. This work introduces RebaseDL, a static analysis that finds profitable and legal region-based data layout transformation opportunities that improve access locality. These opportunities are found within code regions that exhibit data reuse. Going beyond structure splicing, RebaseDL also identifies transformation opportunities that do not involve structure types, that is, it identifies data packing transformations. The analysis is implemented in LLVM and it detects multiple transformation opportunities within the SPEC CPU benchmark suite, where the transformation obtains speedups of up to 1.34x for transformed regions.
References
[1]
[n. d.]. LLVM Block Frequency Terminology. https://llvm.org/docs/BlockFrequencyTerminology.html
[2]
[n. d.]. LLVM Loop Terminology. https://llvm.org/docs/LoopTerminology.html
[3]
Olaf Bachmann, Paul S. Wang, and Eugene V. Zima. 1994. Chains of Recurrences—a Method to Expedite the Evaluation of Closed-Form Functions. In International Symposium on Symbolic and Algebraic Computation (ISSAC). Oxford, United Kingdom. 242–249. https://doi.org/10.1145/190347.190423
[4]
Rodrigo Bruno, Vojin Jovanovic, Christian Wimmer, and Gustavo Alonso. 2021. Compiler-Assisted Object Inlining with Value Fields. In International Conference on Programming Language Design and Implementation (PLDI). Virtual, Canada. 128–141. https://doi.org/10.1145/3453483.3454034
[5]
Trishul M. Chilimbi, Bob Davidson, and James R. Larus. 1999. Cache-Conscious Structure Definition. In International Conference on Programming Language Design and Implementation (PLDI). Atlanta, Georgia, USA. 13–24. https://doi.org/10.1145/301618.301635
[6]
Stephen Curial, Peng Zhao, Jose Nelson Amaral, Yaoqing Gao, Shimin Cui, Raul Silvera, and Roch Archambault. 2008. MPADS: Memory-Pooling-Assisted Data Splitting. In International Symposium on Memory Management (ISMM). Tucson, AZ, USA. 101–110. https://doi.org/10.1145/1375634.1375649
[7]
Karim Esseghir. 1993. Improving Data Locality for Caches. Master’s thesis. Rice University.
[8]
T. Gleixner and I. Molnar. [n. d.]. Linux Perf. https://perf.wiki.kernel.org/index.php/Main_Page
[9]
Google. 2013. Benchmark. https://github.com/google/benchmark
[10]
Kazushige Goto and Robert A. van de Geijn. 2008. Anatomy of High-Performance Matrix Multiplication. ACM Trans. Math. Software, 34, 3 (2008), May, 1–25. https://doi.org/10.1145/1356052.1356053
[11]
R. Hundt, S. Mannarswamy, and D. Chakrabarti. 2006. Practical structure layout optimization and advice. In International Symposium on Code Generation and Optimization (CGO). New York, New York, USA. 233–244. https://doi.org/10.1109/CGO.2006.29
[12]
Chris Lattner and Vikram Adve. 2004. LLVM: A Compilation Framework for Lifelong Program Analysis and Transformation. In International Symposium on Code Generation and Optimization (CGO). San Jose, CA, USA. 75–88. https://doi.org/10.1109/CGO.2004.1281665
[13]
Chris Lattner and Vikram Adve. 2005. Automatic Pool Allocation: Improving Performance by Controlling Data Structure Layout in the Heap. In International Conference on Programming Language Design and Implementation (PLDI). Chicago, IL, USA. 129–142. https://doi.org/10.1145/1065010.1065027
[14]
Rahman Lavaee. 2016. The Hardness of Data Packing. In Symposium on Principles of Programming Languages (POPL). St. Petersburg, FL, USA. 232–242. https://doi.org/10.1145/2837614.2837669
[15]
Xu Liu, Kamal Sharma, and John Mellor-Crummey. 2014. ArrayTool: A Lightweight Profiler to Guide Array Regrouping. In International Conference on Parallel Architectures and Compilation Techniques (PACT). Edmonton, AB, Canada. 405–416. https://doi.org/10.1145/2628071.2628102
[16]
Sandya S. Mannarswamy, Ramaswamy Govindarajan, and Rishi Surendran. 2009. Region Based Structure Layout Optimization by Selective Data Copying. In International Conference on Parallel Architectures and Compilation Techniques (PACT). Raleigh, North Carolina, USA. 338–347. https://doi.org/10.1109/PACT.2009.43
[17]
Erez Petrank and Dror Rawitz. 2002. The Hardness of Cache Conscious Data Placement. In Symposium on Principles of Programming Languages (POPL). Portland, Oregon. 101–112. https://doi.org/10.1145/503272.503283
[18]
Sebastian Pop, Albert Cohen, and Georges-André Silber. 2005. Induction Variable Analysis with Delayed Abstractions. In International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC). Barcelona, Spain. 218–232. https://doi.org/10.1007/11587514_15
[19]
Caio Salvador Rohwedder, João P. L. de Carvalho, and José Nelson Amaral. 2024. Artifact of "Region-Based Data Layout via Data Reuse Analysis". Zenodo. https://doi.org/10.5281/zenodo.10457086
[20]
Caio Salvador Rohwedder, Nathan Henderson, João P. L. De Carvalho, Yufei Chen, and José Nelson Amaral. 2023. To Pack or Not to Pack: A Generalized Packing Analysis and Transformation. In International Symposium on Code Generation and Optimization (CGO). Montréal, QC, Canada. 14–27. https://doi.org/10.1145/3579990.3580024
[21]
O. Temam, E. D. Granston, and W. Jalby. 1993. To Copy or Not to Copy: A Compile-Time Technique for Assessing When Data Copying Should Be Used to Eliminate Cache Conflicts. In ACM/IEEE Conference on Supercomputing. Portland, Oregon, USA. 410–419. https://doi.org/10.1145/169627.169762
[22]
Dan Terpstra, Heike Jagode, Haihang You, and Jack Dongarra. 2010. Collecting Performance Data with PAPI-C. In Tools for High Performance Computing. Berlin, Heidelberg. 157–173. https://doi.org/10.1007/978-3-642-11261-4_11
[23]
Christian Wimmer and Hanspeter Mössenböck. 2008. Automatic Array Inlining in Java Virtual Machines. In International Symposium on Code Generation and Optimization (CGO). Boston, MA, USA. 14–23. https://doi.org/10.1145/1356058.1356061
[24]
JiaNian Yan, JiangZhou He, WenGuang Chen, Pen-Chung Yew, and WeiMin Zheng. 2011. ASLOP: A field-access affinity-based structure data layout optimizer. Science China Information Sciences, 54, 9 (2011), 1769–1783. https://doi.org/10.1007/s11432-011-4265-0
[25]
Louis Ye, Mieszko Lis, and Alexandra Fedorova. 2019. A Unifying Abstraction for Data Structure Splicing. In International Symposium on Memory Systems (MEMSYS). Washington, District of Columbia, USA. 173–183. https://doi.org/10.1145/3357526.3357548
[26]
Chao Yu, Probir Roy, Yuebin Bai, Hailong Yang, and Xu Liu. 2018. LWPTool: A Lightweight Profiler to Guide Data Layout Optimization. Transactions on Parallel and Distributed Systems (TPDS), 29, 11 (2018), 2489–2502. https://doi.org/10.1109/TPDS.2018.2840992
[27]
Peng Zhao, Shimin Cui, Yaoqing Gao, Raúl Silvera, and José Nelson Amaral. 2007. Forma: A Framework for Safe Automatic Array Reshaping. ACM Transactions on Programming Languages and Systems, 30, 1 (2007), nov, 2–es. https://doi.org/10.1145/1290520.1290522
[28]
Yutao Zhong, Maksim Orlovich, Xipeng Shen, and Chen Ding. 2004. Array Regrouping and Structure Splitting Using Whole-Program Reference Affinity. In International Conference on Programming Language Design and Implementation (PLDI). Washington DC, USA. 255–266. https://doi.org/10.1145/996841.996872
Index Terms
- Region-Based Data Layout via Data Reuse Analysis
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Published In
February 2024
261 pages
ISBN:9798400705076
DOI:10.1145/3640537
- General Chair:
- Gabriel Rodríguez,
- Program Chairs:
- P. Sadayappan,
- Aravind Sukumaran-Rajam
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Published: 20 February 2024
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