ISPD

It is our great pleasure to welcome you to the 2011 International Symposium on Physical Design (ISPD) held at Hotel Mar Monte, Santa Barbara, California. Evolving from a series of intermittent ACM/SIGDA Physical Design Workshops, ISPD has established itself as the premier forum for exchanging ideas and results on VLSI physical design. In the past, ISPD showcased seminal papers that advanced the state-of-the-art of physical design technology. In addition, the celebrated ISPD contests inspired numerous research studies that led to technical breakthroughs.

This year's symposium continues its dedication to high-quality despite its small scale. Papers submitted from all over the world are carefully reviewed by highly experienced technical program committee members and external reviewers. After a rigorous selection procedure that involves vigorous discussions, only a small number of papers are accepted. These papers cover various aspects of physical design, from traditional placement and routing to issues related to the most leading-edge technology, such as variability and manufacturability. These papers are complemented by invited talks by prestigious speakers.

The symposium begins with a keynote speech by Professor Massoud Pedram from University of Southern California. Professor Pedram is a highly accomplished and world-renowned scholar on electronic design automation as well as a former general chair of ISPD. His speech addresses power-efficiency of modern and future VLSI designs. A feature event in this year is the commemorative session for Professor Ernest Kuh, a groundbreaking researcher/educator on physical design and a Phil Kaufman Award recipient. We are delighted to have a talk by Professor Kuh and retrospections on his accomplishments by his former students and associate. Tuesday includes invited talks on 3D ICs, placement and DFM routing, given by speakers from Intel, Tezzaron, SpringSoft and Mentor Graphics. The physical design contest result is announced in the afternoon of Tuesday. This year's contest is a revisit to placement, a core physical design problem, with particular emphasis on routability, which is a growing challenge to sub-65nm technology chip designs. Along with the contest, a new set of industrial benchmarks are released and will facilitate scientific evaluations of related research results. Finally, Wednesday features invited talks on design for manufacturing by renowned academic scholar and industrial expert.