ICCAD '16: Proceedings of the 35th International Conference on Computer-Aided Design
2016 Proceeding- General Chair:
- Frank Liu
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Abstract
Jointly sponsored by IEEE and ACM, ICCAD is the premier forum to explore emerging technology challenges, present cutting-edge R&D solutions, record theoretical and empirical advances, and identify future roadmaps for design automation and other system-on-chip research areas.
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Scope - quality retaining display rendering workload scaling based on user-smartphone distance
NVSim-CAM
Design technology for fault-free and maximally-parallel wavelength-routed optical networks-on-chip
Fast generation of lexicographic satisfiable assignments
Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits
A flash-based digital circuit design flow
MrDP
OWARU
Detailed placement for modern FPGAs using 2D dynamic programming
Security and privacy threats to on-chip non-volatile memories and countermeasures
Security engineering of nanostructures and nanomaterials
Caffeine
Re-architecting the on-chip memory sub-system of machine-learning accelerator for embedded devices
A data locality-aware design framework for reconfigurable sparse matrix-vector multiplication kernel
Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing
A new tightly-coupled transient electro-thermal simulation method for power electronics
A tensor-based volterra series black-box nonlinear system identification and simulation framework
Efficient statistical analysis for correlated rare failure events via asymptotic probability approximation
Duplex
Improved flop tray-based design implementation for power reduction
RC-aware global routing
Scalable, high-quality, SAT-based multi-layer escape routing
Redistribution layer routing for integrated fan-out wafer-level chip-scale packages
The architecture value engine: measuring and delivering sustainable SoC improvement
Circuit valorization in the IC design ecosystem
Interconnect-aware device targeting from PPA perspective
Measuring progress and value of IC implementation technology
Provably secure camouflaging strategy for IC protection
CamoPerturb
Chip editor
Arbitrary streaming permutations with minimum memory and latency
Multibank memory optimization for parallel data access in multiple data arrays
Allocation of multi-bit flip-flops in logic synthesis for power optimization
Model-based design of resource-efficient automotive control software
Testing automotive embedded systems under X-in-the-loop setups
Efficient statistical validation of machine learning systems for autonomous driving
CONVINCE
Overview of the 2016 CAD contest at ICCAD
ICCAD-2016 CAD contest in large-scale identical fault search
ICCAD-2016 CAD contest in non-exact projective NPNP boolean matching and benchmark suite
ICCAD-2016 CAD contest in pattern classification for integrated circuit design space analysis and benchmark suite
OpenDesign flow database: the infrastructure for VLSI design and design automation research
Malicious LUT
On detecting delay anomalies introduced by hardware trojans
An optimization-theoretic approach for attacking physical unclonable functions
LRR-DPUF
Enabling online learning in lithography hotspot detection with information-theoretic feature optimization
Incorporating cut redistribution with mask assignment to enable 1D gridded design
VCR
DSA-compliant routing for two-dimensional patterns using block copolymer lithography
The art of semi-formal bug hunting
Compiled symbolic simulation for systemC
Exact diagnosis using boolean satisfiability
Efficient and accurate analysis of single event transients propagation using SMT-based techniques
Power delivery in 3D packages
Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration
Energy-efficient and reliable 3D network-on-chip (NoC): architectures and optimization algorithms
The hype, myths, and realities of testing 3D integrated circuits
TASA
research-article
Splitting functions in code management on scratchpad memories
As the number of cores increases, cache-based memory hierarchy is becoming a major problem in terms of the scalability and energy consumption. Software-managed scratchpad memories (SPM) is a scalable alternative to caches, but the benefit comes at the ...
Adaptive performance prediction for integrated GPUs
Energy-efficient fault tolerance approach for internet of things applications
Critical path isolation for time-to-failure extension and lower voltage operation
Control synthesis and delay sensor deployment for efficient ASV designs
Performance driven routing for modern FPGAs
UTPlaceF: a routability-driven FPGA placer with physical and congestion aware packing
RippleFPGA
GPlace
Resiliency in dynamically power managed designs
Dynamic reliability management for near-threshold dark silicon processors
A cross-layer approach for resiliency and energy efficiency in near threshold computing
Design space exploration of drone infrastructure for large-scale delivery services
Multi-objective design optimization for flexible hybrid electronics
KCAD
research-article
Autonomous sensor-context learning in dynamic human-centered internet-of-things environments
Human-centered Internet-of-Things (IoT) applications utilize computational algorithms such as machine learning and signal processing techniques to infer knowledge about important events such as physical activities and medical complications. The ...
Formulating customized specifications for resource allocation problem of distributed embedded systems
A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops
Efficient memory compression in deep neural networks using coarse-grain sparsification for speech applications
Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design
Architectural-space exploration of approximate multipliers
Design of power-efficient approximate multipliers for approximate artificial neural networks
Automated error prediction for approximate sequential circuits
Approximation-aware rewriting of AIGs for error tolerant applications
Properties first? a new design methodology for hardware, and its perspectives in safety analysis
Where formal verification can help in functional safety analysis
Formal approaches to design of active cell balancing architectures in battery management systems
How much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node?
A novel unified dummy fill insertion framework with SQP-based optimization method
Efficient yield estimation through generalized importance sampling with application to NBL-assisted SRAM bitcells
Are proximity attacks a threat to the security of split manufacturing of integrated circuits?
Making split-fabrication more secure
A machine learning approach to fab-of-origin attestation
OpenRAM: an open-source memory compiler
A hardware-based technique for efficient implicit information flow tracking
Imprecise security
Encasing block ciphers to foil key recovery attempts via side channel
Security of neuromorphic computing
Generation and use of statistical timing macro-models considering slew and load variability
TinySPICE plus
PieceTimer
A fast layer elimination approach for power grid reduction
A deterministic approach to stochastic computation
Control-fluidic CoDesign for paper-based digital microfluidic biochips
Neural networks designing neural networks
Error recovery in a micro-electrode-dot-array digital microfluidic biochip?
Privacy protection via appliance scheduling in smart homes
Framework designs to enhance reliable and timely services of disaster management systems
Analysis of production data manipulation attacks in petroleum cyber-physical systems
Security challenges in smart surveillance systems and the solutions based on emerging nano-devices
Fast physics-based electromigration checking for on-die power grids
Exploring aging deceleration in FinFET-based multi-core systems
An efficient and accurate algorithm for computing RC current response with applications to EM reliability evaluation
Voltage-based electromigration immortality check for general multi-branch interconnects
Exploiting randomness in sketching for efficient hardware implementation of machine learning applications
Making neural encoding robust and energy efficient
Statistical methodology to identify optimal placement of on-chip process monitors for predicting fmax
BugMD
ODESY
Delay-optimal technology mapping for in-memory computing using ReRAM devices
Reconfigurable in-memory computing with resistive memory crossbar
Exploiting ferroelectric FETs for low-power non-volatile logic-in-memory circuits
Approximation knob
IC thermal analyzer for versatile 3-D structures using multigrid preconditioned krylov methods
BoostNoC
QScale
Synthesis of statically analyzable accelerator networks from sequential programs
Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory
Efficient synthesis of graph methods
Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs
Cascade2D
SAINT
From biochips to quantum circuits: computer-aided design for emerging technologies
Multilevel design understanding
Cited By
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Aigner M, Kissner M, Päsler F, Del Bino L, Schröder H and Chen R (2024). Connect-A-PIC: an open-source automated photonic circuit design and simulation platform for fast iteration and education Optical Interconnects XXIV, 10.1117/12.2692187, 9781510670440, (26)
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Sim H and Lee J (2020). Bitstream-Based Neural Network for Scalable, Efficient, and Accurate Deep Learning Hardware, Frontiers in Neuroscience, 10.3389/fnins.2020.543472, 14
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Nie H, Li H, Yang Q and Li D (2018). Effect of structure and stability of active phase on catalytic performance of hydrotreating catalysts, Catalysis Today, 10.1016/j.cattod.2018.05.006, 316, (13-20), Online publication date: 1-Oct-2018.
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Pan D, Lin Y, Xu X, Ou J, Gallagher E and Buck P (2017). Machine learning for mask/wafer hotspot detection and mask synthesis Photomask Technology, 10.1117/12.2282943, 9781510613768, (10)