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A C Subset for Ergonomic Source-to-Source Analyses and Transformations
Modern compiled software, written in languages such as C, relies on complex compiler infrastructure. However, developing new transformations and improving existing ones can be challenging for researchers and engineers. Often, transformations must be ...
Design Space Exploration of HPC Systems with Random Forest-based Bayesian Optimization
Nowadays, High-Performance Computing (HPC) systems need to deliver computational performance by processing complex applications and workloads at high speeds in parallel. To provide computing power, Multiprocessor System-on-Chip, the main design paradigm,...
NQC²: A Non-Intrusive QEMU Code Coverage Plugin
Code coverage analysis has become a standard approach in software development, facilitating the assessment of test suite effectiveness, the identification of under-tested code segments, and the discovery of performance bottlenecks. When code coverage of ...
Integration of RISC-V Page Table Walk in gem5 SE Mode
gem5 is a popular architectural simulator, for both academic and industrial researchers. It can be used in two configurations: Full System mode and Syscall Emulation mode. The former requires running a real kernel to achieve realistic results, at the ...
Makinote: An FPGA-Based HW/SW Platform for Pre-Silicon Emulation of RISC-V Designs
- Elias Perdomo,
- Alexander Kropotov,
- Francelly Katherine Cano Ladino,
- Syed Zafar,
- Teresa Cervero,
- Xavier Martorell Bofill,
- Behzad Salami
Emulating chip functionality before silicon production is crucial, especially with the increasing prevalence of RISC-V-based designs. FPGAs are promising candidates for such purposes due to their high-speed and reconfigurable architecture. In this paper,...
Modeling methodology for multi-die chip design based on gem5/SystemC co-simulation
- Fabian Schätzle,
- Carlos Falquez,
- Stefan Heinen,
- Nam Ho,
- Antoni Portero,
- Estela Suarez,
- Johannes Van Den Boom,
- Stefan Van Waasen
The paper introduces a modeling methodology aimed at thoroughly exploring the design space of multi-die chip architecture tailored for High-Performance Computing (HPC). For accurate simulations, we leverage the capabilities of gem5’s Ruby for its robust ...
Using Source-to-Source to Target RISC-V Custom Extensions: UVE Case-Study
Hardware specialization is seen as a promising venue for improving computing efficiency, with reconfigurable devices as excellent deployment platforms for application-specific architectures. One approach to hardware specialization is via the popular ...
Index Terms
- Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design
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Acceptance Rates
Year | Submitted | Accepted | Rate |
---|---|---|---|
RAPIDO '17 | 12 | 6 | 50% |
RAPIDO '15 | 16 | 8 | 50% |
Overall | 28 | 14 | 50% |