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Radiation-induced soft errors are getting worse in digital systems manufactured in advanced technologies. Stringent data integrity and availability requirements of enterprise computing and networking applications demand special attention to soft errors ...

We will mainly address here the "alter ego" of quality, which is reliability, and is becoming a growing concern for designers using the latest technologies. After the DFM nodes in 90nm and 65nm, we are entering the DFR area, or Design For Reliability ...

With the increasing need for design specific yield optimization in nanometer technologies, it is becoming increasingly important to accelerate the identification of the root cause of systematic defects under very tight test cost constraints. This talk ...

This paper proposes the fuse, a technique to anticipate failures due to degradation in any ALU (Arithmetic Logic Unit), and particularly in an adder. The fuse consists of a replica of the weakest transistor in the adder and the circuitry required to ...

This paper presents Adaptive Variation-and-Error- Resilient Agent (AVERA), an approach to address the challenge of designing reliable systems in the presence of soft errors and variations. AVERA extends our previous Built-In Soft Error Resilience (BISER)...

High defect rate in emerging nano-devices mandates new computational models that can tolerate defects thereby rendering reliability of operation and reasonable manufacturing yield. In a bottom-up system design approach using nano-crossbar applications ...

Fault-tolerant design of Network-on-chip communication architectures requires the addressing of issues pertaining to different elements described at different levels of design abstraction -- these may be specific to architecture, interconnection, ...

In this paper we propose a novel error control scheme to cope with errors affecting the communication links of a NoC. Our scheme can be configured in Correction Mode, Detection Mode, and Mixed Mode, depending on the particular application, thus allowing ...

This paper proposes an analytical model to assess Reliability Factor of an NoC based System-on-Chip design. Reliability Factor is the probability that faults in the NoC infrastructure can be recovered without any effect on system functionality. The ...

In this paper we propose an on-line fault detection architecture for bijective Substitution Boxes used in cryptographic circuits. Concurrent fault detection is important not only to protect the encryption/decryption process from random and production ...

Latchup is a short-circuit that can be triggered in CMOS ICs when a current pulse is produced by parasitic perturbations. It is usually regarded as very disturbing for reliability, especially in space applications where it is triggered by ionizing ...

In this paper we present an efficient design technique for implementing the Elliptic Curve Cryptographic (ECC) Scheme in FPGAs. Our technique is based on a novel and efficient implementation of modular multiplication which is the core operation of ECC. ...

An assertion-based monitoring system was implemented to enforce the operation of a FPGA coprocessing engine, which is part of a dependable workstation. The monitor was built in VHDL using simple state machines. Concurrent error detection is an important ...

Commercial Off-The-Shelf (COTS) electronic components are attractive for space applications. However, fault-tolerant architectures are required to cope with the Single Event Effect sensitivity of these components. CNES has developed a methodology, and ...

This paper presents a new approach based on a watchdog infrastructure intellectual property (I-IP) core to detect control-flow faults that affect CPU execution time. More precisely, this approach aims at detecting those faults that change the expected ...

Processors are very common components in current digital systems and to assess their reliability is an essential task during the design process. In this paper a new fault injection solution to measure SEU sensitivity in processors is presented. It ...

The reliability of Systems-on-Chip (SoCs) is very important with respect to their use in different types of critical applications. Several fault tolerance techniques have been proposed to improve their fault detection and correction capabilities. These ...

Asynchronous circuits are often claimed as being an interesting alternative to design robust systems against faults. In this study, a method is proposed to model the behavior of Quasi Delay Insensitive (QDI) asynchronous circuits in the presence of SEUs ...

Embedded system design is especially demanding in terms of requirements that need to be satisfied, e.g. real-time processing, cost effectiveness, low energy consumption and reliable operation. These requirements have to be properly balanced until a ...

Infant Mortality problems have been around for a long time (maybe that is why sometimes we have a shorter warranty period for many electronic products). Anyway, the explanation of infant mortality is that these are left over (or latent) defects. Defects ...

Circuit failure prediction predicts the occurrence of a circuit failure before errors actually appear in system data and states. This is in contrast to classical error detection where a failure is detected after errors appear in system data and states. ...

Silicon technology evolution over the last four decades has yielded an exponential increase in integration densities with steady improvements of performance and power consumption at each technology generation. This steady progress has created a sense of ...

In the accelerated soft-error rate (SER) testing of embedded SRAMs usually only a few samples of a given device are tested, often only for a checkerboard data pattern and at the nominal supply voltage. In this paper it is demonstrated, using a 90-nm ...

This paper presents a methodology for analyzing the behavior of nanometer technologies regarding "Multiple Event Transients" (MET) caused by nuclear reaction induced by atmospheric neutrons. For the first time, currents collected by several sensitive ...

We tested a commercial 1Gbit 90nm NAND memory under exposure to a constant flux of heavy ions, aiming to study its behaviour in the space environment. We identified and classified different types of errors under various operating conditions. We observed ...

Soft errors caused by ionizing radiation have emerged as a major concern for current generation of CMOS echnologies and the trend is expected to get worse. A significant fraction of soft errors in semiconductor has been reported to never lead to a ...