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- research-articleJuly 2024
Partial Solution Based Constraint Solving Cache in Symbolic Execution
Proceedings of the ACM on Software Engineering (PACMSE), Volume 1, Issue FSEArticle No.: 110, Pages 2493–2514https://doi.org/10.1145/3660817Constraint solving is one of the main challenges for symbolic execution. Caching is an effective mechanism to reduce the number of the solver invocations in symbolic execution and is adopted by many mainstream symbolic execution engines. However, caching ...
- research-articleApril 2024
Energy and Cache Aware Routing for Socially Aware Networking in the Big Data Environment
Journal of Signal Processing Systems (JSPS), Volume 96, Issue 2Feb 2024, Pages 169–178https://doi.org/10.1007/s11265-024-01914-xAbstractIn the big data environment, Socially Aware Networking (SAN) can obtain a large amount of status data and social contacts of network nodes. If the information is fully analyzed and utilized, it will effectively improve the energy efficiency and ...
- research-articleApril 2024
Volley: Accelerating Write-Read Orders in Disaggregated Storage
EuroSys '24: Proceedings of the Nineteenth European Conference on Computer SystemsApril 2024, Pages 657–673https://doi.org/10.1145/3627703.3650090Modern data centers deploy disaggregated storage systems (e.g., NVMe over Fabrics, NVMe-oF) for fine-grained resource elasticity and high resource utilization. A client-side writeback cache is used to absorb writes and buffer frequently accessed data, ...
- research-articleApril 2024JUST ACCEPTED
Intermediate Address Space: virtual memory optimization of heterogeneous architectures for cache-resident workloads
ACM Transactions on Architecture and Code Optimization (TACO), Just Accepted https://doi.org/10.1145/3659207The increasing demand for computing power and the emergence of heterogeneous computing architectures have driven the exploration of innovative techniques to address current limitations in both the compute and memory subsystems. One such solution is the ...
- research-articleApril 2024
An efficient content replacement policy to retain essential content in information-centric networking based internet of things network
AbstractIn the current scenario, TCP/IP is widely used in the Internet of Things (IoT) for disseminating data, addressing, and controlling traffic. However, the exponential growth of IoT devices has incurred the TCP/IP-based network from mismanagement ...
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- research-articleFebruary 2024
COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications
Journal of Systems Architecture: the EUROMICRO Journal (JOSA), Volume 145, Issue CDec 2023https://doi.org/10.1016/j.sysarc.2023.103022AbstractThe growing trend of pervasive computing has consolidated the everlasting need for power efficient devices. The conventional cache subsystem of general-purpose CPUs, while being able to adapt to many use cases, suffers from energy inefficiencies ...
- ArticleJanuary 2024
Construction of Locality-Aware Algorithms to Optimize Performance of Stencil Codes on Heterogeneous Hardware
AbstractRecently, an increase in code performance has been obtained mainly through parallelism. For codes that implement stencil schemes, parallel processing requires data-intensive exchange. When parallel threads need to communicate, memory bandwidth ...
- research-articleDecember 2023
Flash-Based Solid-State Storage Reduces LDPC Read Retry Scheme
CSAE '23: Proceedings of the 7th International Conference on Computer Science and Application EngineeringOctober 2023, Article No.: 32, Pages 1–6https://doi.org/10.1145/3627915.3628024Flash memory, with its high performance and low power consumption, has been widely applied in various fields. The increasing storage density of flash memory has led to a gradual increase in Bit Error Rate (BER). Given the users' requirement for data ...
- research-articleDecember 2023
Hardware Support for Constant-Time Programming
MICRO '23: Proceedings of the 56th Annual IEEE/ACM International Symposium on MicroarchitectureOctober 2023, Pages 856–870https://doi.org/10.1145/3613424.3623796Side-channel attacks are one of the rising security concerns in modern computing platforms. Observing this, researchers have proposed both hardware-based and software-based strategies to mitigate side-channel attacks, targeting not only on-chip caches ...
- research-articleDecember 2023
Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings
- Konstantinos Kanellopoulos,
- Rahul Bera,
- Kosta Stojiljkovic,
- F. Nisa Bostanci,
- Can Firtina,
- Rachata Ausavarungnirun,
- Rakesh Kumar,
- Nastaran Hajinazar,
- Mohammad Sadrosadati,
- Nandita Vijaykumar,
- Onur Mutlu
MICRO '23: Proceedings of the 56th Annual IEEE/ACM International Symposium on MicroarchitectureOctober 2023, Pages 1196–1212https://doi.org/10.1145/3613424.3623789Conventional virtual memory (VM) frameworks enable a virtual address to flexibly map to any physical address. This flexibility necessitates large data structures to store virtual-to-physical mappings, which leads to high address translation latency and ...
- research-articleDecember 2023
Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources
- Konstantinos Kanellopoulos,
- Hong Chul Nam,
- Nisa Bostanci,
- Rahul Bera,
- Mohammad Sadrosadati,
- Rakesh Kumar,
- Davide Basilio Bartolini,
- Onur Mutlu
MICRO '23: Proceedings of the 56th Annual IEEE/ACM International Symposium on MicroarchitectureOctober 2023, Pages 1178–1195https://doi.org/10.1145/3613424.3614276Address translation is a performance bottleneck in data-intensive workloads due to large datasets and irregular access patterns that lead to frequent high-latency page table walks (PTWs). PTWs can be reduced by using (i) large hardware TLBs or (ii) ...
- research-articleDecember 2023
Uncore Encore: Covert Channels Exploiting Uncore Frequency Scaling
MICRO '23: Proceedings of the 56th Annual IEEE/ACM International Symposium on MicroarchitectureOctober 2023, Pages 843–855https://doi.org/10.1145/3613424.3614259Modern processors dynamically adjust clock frequencies and voltages to reduce energy consumption. Recent Intel processors separate the uncore frequency from the core frequency, using Uncore Frequency Scaling (UFS) to adapt the uncore frequency to ...
- research-articleDecember 2023
CLIP: Load Criticality based Data Prefetching for Bandwidth-constrained Many-core Systems
MICRO '23: Proceedings of the 56th Annual IEEE/ACM International Symposium on MicroarchitectureOctober 2023, Pages 714–727https://doi.org/10.1145/3613424.3614245Hardware prefetching is a latency-hiding technique that hides the costly off-chip DRAM accesses. However, state-of-the-art prefetchers fail to deliver performance improvement in the case of many-core systems with constrained DRAM bandwidth. For SPEC ...
- research-articleDecember 2023
VMIFresh: Efficient and fresh caches for virtual machine introspection
Computers and Security (CSEC), Volume 135, Issue CDec 2023https://doi.org/10.1016/j.cose.2023.103527AbstractVirtual machine introspection (VMI) is the process of extracting knowledge about the inner state of a virtual machine from the outside. Traditional passive introspection mechanisms have proved themselves ineffective in many application domains ...
- ArticleNovember 2023
Combining Cache and Refresh to Optimize SSD Read Performance Scheme
Advanced Parallel Processing TechnologiesAug 2023, Pages 113–129https://doi.org/10.1007/978-981-99-7872-4_7AbstractIn the era of continuous advances in flash technology, the storage density of NAND flash memory is increasing, but the availability of data is declining. In order to improve data availability, low-density parity check codes (LDPC), which have been ...
- ArticleNovember 2023
High Performance Instruction Fetch Structure within a RISC-V Processor for Use in Harsh Environments
Embedded Computer Systems: Architectures, Modeling, and SimulationJul 2023, Pages 255–268https://doi.org/10.1007/978-3-031-46077-7_17AbstractAn increasing number of sensors and actuators are being used in today’s high-tech drilling tools to further optimise the drilling process. Each sensor and actuator either generates data that needs to be processed or requires real-time input ...
- research-articleOctober 2023
An edge re-ordering based acceleration architecture for improving data locality in graph analytics applications
Microprocessors & Microsystems (MSYS), Volume 102, Issue COct 2023https://doi.org/10.1016/j.micpro.2023.104895AbstractData structure is the key in Edge Computing where various types of data are continuously generated by ubiquitous devices. Within all common data structures, graphs are used to express relationships and dependencies among human identities, objects,...
- review-articleJuly 2023
A survey of software techniques to emulate heterogeneous memory systems in high-performance computing
AbstractHeterogeneous memory will be involved in several upcoming platforms on the way to exascale. Combining technologies such as HBM, DRAM and/or NVDIMM allows to tackle the needs of different applications in terms of bandwidth, latency or ...
Highlights- Survey of the current landscape of the memory subsystem in HPC platforms.
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- research-articleJune 2023
Lightweight Register File Caching in Collector Units for GPUs
GPGPU '23: Proceedings of the 15th Workshop on General Purpose Processing Using GPUFebruary 2023, Pages 27–33https://doi.org/10.1145/3589236.3589245Modern GPUs benefit from a sizable Register File (RF) to provide fine-grained thread switching. As the RF is huge and accessed frequently, it consumes a considerable share of the dynamic energy of the GPU. Designing a large, high-throughput RF with low ...
- research-articleMay 2023
High Speed Multi-channel Data Cache Design Based on DDR3 SDRAM
AIPR '22: Proceedings of the 2022 5th International Conference on Artificial Intelligence and Pattern RecognitionSeptember 2022, Pages 193–196https://doi.org/10.1145/3573942.3573972With the rapid development of microelectronics technology, the amount of data information is becoming larger and larger, and the speed of data processing is becoming higher and higher. In order to meet the needs of today's data cache and solve a series ...