Flash-Based Solid-State Storage Reduces LDPC Read Retry Scheme
Authors: 
Jinli Chen, Peixuan Li, Ping XieAuthors Info & Claims
Jinli Chen, Peixuan Li, Ping XieAuthors Info & ClaimsArticle No.: 32, Pages 1 - 6
Abstract
Flash memory, with its high performance and low power consumption, has been widely applied in various fields. The increasing storage density of flash memory has led to a gradual increase in Bit Error Rate (BER). Given the users' requirement for data accuracy, the reliability of flash memory has become a research focus. Currently, a common approach to achieve data error correction is by introducing error-correcting code modules. Among them, Low-Density Parity-Check (LDPC) codes are widely adopted due to their excellent error correction capability. However, using LDPC codes directly for error correction can introduce significant latency. To reduce the decoding latency of LDPC codes, this paper proposes a combined approach of refreshing and caching. Experimental results demonstrate that compared to the original approach, this scheme can achieve a maximum reduction of 28% in average response time and a maximum improvement of 63% in IOPS.
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Index Terms
- Flash-Based Solid-State Storage Reduces LDPC Read Retry Scheme
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October 2023
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Published: 21 December 2023
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CSAE 2023
CSAE 2023: The 7th International Conference on Computer Science and Application Engineering
October 17 - 19, 2023
Virtual Event, China
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