Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
10.1145/3061639.3062309acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
research-article

Reducing LDPC Soft Sensing Latency by Lightweight Data Refresh for Flash Read Performance Improvement

Published: 18 June 2017 Publication History

Abstract

In order to relieve reliability problem caused by technology scaling, LDPC codes have been widely applied in flash memories to provide high error correction capability. However, LDPC read performance slowdown along with data retention largely weakens the access speed advantage of flash memories. This paper considers to apply the concept of refresh, that were used for flash lifetime improvement, to optimize flash read performance. Exploiting data read characteristics, this paper proposes LDR, a lightweight data refresh method, that aggressively corrects errors in read-hot pages with long read latency and reprograms error-free data into new pages. Experimental results show that LDR can achieve 29% read performance improvement with only 0.2% extra P/E cycles on average, which causes negligible overhead on flash lifetime.

References

[1]
MSR cambridge traces. http://iotta.snia.org/tracetypes/3. Accessed: 2016--11.
[2]
Samsung 750 EVO SSD review 2016. http://www.tomshardware.com/reviews/samsung-750-evo-ssd,4467.html. Accessed: 2016--11.
[3]
UMass trace repository. http://traces.cs.umass.edu/index.php/Storage/Storage. Accessed: 2016--11.
[4]
N. Agrawal, V. Prabhakaran, T. Wobber, J. D. Davis, M. S. Manasse, and R. Panigrahy. Design tradeoffs for SSD performance. In USENIX Annual Technical Conference, pages 57--70, 2008.
[5]
Y. Cai, Y. Luo, E. F. Haratsch, K. Mai, and O. Mutlu. Data retention in MLC NAND flash memory: Characterization, optimization, and recovery. In 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), pages 551--563. IEEE, 2015.
[6]
Y. Cai, G. Yalcin, O. Mutlu, E. F. Haratsch, A. Cristal, O. S. Unsal, and K. Mai. Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime. In Computer Design (ICCD), 2012 IEEE 30th International Conference on, pages 94--101. IEEE, 2012.
[7]
Y. Di, L. Shi, K. Wu, and C. J. Xue. Exploiting process variation for retention induced refresh minimization on flash memory. In 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 391--396. IEEE, 2016.
[8]
J. Guo, W. Wen, J. Hu, D. Wang, H. Li, and Y. Chen. Flexlevel NAND flash storage system design to reduce LDPC latency. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016.
[9]
Q. Li, L. Shi, C. J. Xue, K. Wu, C. Ji, Q. Zhuge, and E. H.-M. Sha. Access characteristic guided read and write cost regulation for performance improvement on flash memory. In Proceedings of the 14th Usenix Conference on File and Storage Technologies, pages 125--132. USENIX Association, 2016.
[10]
R.-S. Liu, M.-Y. Chuang, C.-L. Yang, C.-H. Li, K.-C. Ho, and H.-P. Li. Improving read performance of NAND flash SSDs by exploiting error locality. IEEE Transactions on Computers, 65(4):1090--1102, 2016.
[11]
Y. Luo, Y. Cai, S. Ghose, J. Choi, and O. Mutlu. WARM: Improving NAND flash memory lifetime with write-hotness aware retention management. In 2015 31st Symposium on Mass Storage Systems and Technologies (MSST), pages 1--14. IEEE, 2015.
[12]
D. J. MacKay. Good error-correcting codes based on very sparse matrices. Information Theory, IEEE Transactions on, 45(2):399--431, 1999.
[13]
M. Murugan and D. H. Du. Rejuvenator: A static wear leveling algorithm for NAND flash memory with minimized overhead. In 2011 IEEE 27th Symposium on Mass Storage Systems and Technologies (MSST), pages 1--12. IEEE, 2011.
[14]
Y. Pan, G. Dong, Q. Wu, and T. Zhang. Quasi-nonvolatile SSD: Trading flash memory nonvolatility to improve storage system performance for enterprise applications. In High Performance Computer Architecture (HPCA), 2012 IEEE 18th International Symposium on, pages 1--10. IEEE, 2012.
[15]
B. Shen, Y. Li, Y. Xu, and Y. Pan. A light-weight hot data identification scheme via grouping-based LRU lists. In International Conference on Algorithms and Architectures for Parallel Processing, pages 88--103. Springer, 2015.
[16]
K. Zhao, W. Zhao, H. Sun, X. Zhang, N. Zheng, and T. Zhang. LDPC-in-SSD: making advanced error correction codes work effectively in solid state drives. In Presented as part of the 11th USENIX Conference on File and Storage Technologies (FAST 13), pages 243--256, 2013.

Cited By

View all
  • (2024)Enhancing Data Integrity with Efficient Retention-Refilling Programming SchemesACM SIGAPP Applied Computing Review10.1145/3699839.369984224:3(37-50)Online publication date: 1-Sep-2024
  • (2024)Modeling Retention Errors of 3D NAND Flash for Optimizing Data PlacementACM Transactions on Design Automation of Electronic Systems10.1145/365910129:4(1-24)Online publication date: 16-Apr-2024
  • (2024)On Enhancing Data Integrity with Low-cost Retention-Refillable Programming SchemeProceedings of the 39th ACM/SIGAPP Symposium on Applied Computing10.1145/3605098.3635905(420-427)Online publication date: 8-Apr-2024
  • Show More Cited By

Index Terms

  1. Reducing LDPC Soft Sensing Latency by Lightweight Data Refresh for Flash Read Performance Improvement

      Recommendations

      Comments

      Information & Contributors

      Information

      Published In

      cover image ACM Conferences
      DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017
      June 2017
      533 pages
      ISBN:9781450349277
      DOI:10.1145/3061639
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Sponsors

      In-Cooperation

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 18 June 2017

      Permissions

      Request permissions for this article.

      Check for updates

      Author Tags

      1. Data Refresh
      2. Flash Read Performance
      3. LDPC Codes

      Qualifiers

      • Research-article
      • Research
      • Refereed limited

      Funding Sources

      • National 973 Fundamental Basic Research Program
      • National Science Foundation of China
      • National 863 Program

      Conference

      DAC '17
      Sponsor:

      Acceptance Rates

      Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

      Upcoming Conference

      DAC '25
      62nd ACM/IEEE Design Automation Conference
      June 22 - 26, 2025
      San Francisco , CA , USA

      Contributors

      Other Metrics

      Bibliometrics & Citations

      Bibliometrics

      Article Metrics

      • Downloads (Last 12 months)21
      • Downloads (Last 6 weeks)7
      Reflects downloads up to 23 Dec 2024

      Other Metrics

      Citations

      Cited By

      View all
      • (2024)Enhancing Data Integrity with Efficient Retention-Refilling Programming SchemesACM SIGAPP Applied Computing Review10.1145/3699839.369984224:3(37-50)Online publication date: 1-Sep-2024
      • (2024)Modeling Retention Errors of 3D NAND Flash for Optimizing Data PlacementACM Transactions on Design Automation of Electronic Systems10.1145/365910129:4(1-24)Online publication date: 16-Apr-2024
      • (2024)On Enhancing Data Integrity with Low-cost Retention-Refillable Programming SchemeProceedings of the 39th ACM/SIGAPP Symposium on Applied Computing10.1145/3605098.3635905(420-427)Online publication date: 8-Apr-2024
      • (2024)Adaptive Differential Wearing for Read Performance Optimization on High-Density nand Flash MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.329797143:1(380-393)Online publication date: Jan-2024
      • (2024)CDS: Coupled Data Storage to Enhance Read Performance of 3D TLC NAND Flash MemoryIEEE Transactions on Computers10.1109/TC.2023.333847473:3(694-707)Online publication date: Mar-2024
      • (2024)DIR: Dynamic Request Interleaving for Improving the Read Performance of Aged Solid-State DrivesJournal of Computer Science and Technology10.1007/s11390-023-1601-y39:1(82-98)Online publication date: 30-Jan-2024
      • (2023)Flash-Based Solid-State Storage Reduces LDPC Read Retry SchemeProceedings of the 7th International Conference on Computer Science and Application Engineering10.1145/3627915.3628024(1-6)Online publication date: 17-Oct-2023
      • (2023)ALCod: Adaptive LDPC Coding for 3-D NAND Flash Memory Using Inter-Layer RBER VariationIEEE Transactions on Consumer Electronics10.1109/TCE.2023.331963869:4(1068-1081)Online publication date: Nov-2023
      • (2023)Retention-Aware Read Acceleration Strategy for LDPC-Based NAND Flash MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.328932842:12(4597-4605)Online publication date: Dec-2023
      • (2023)Access Characteristic Guided Partition for Nand Flash-Based High-Density SSDsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.328217542:12(4643-4656)Online publication date: Dec-2023
      • Show More Cited By

      View Options

      Login options

      View options

      PDF

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader

      Media

      Figures

      Other

      Tables

      Share

      Share

      Share this Publication link

      Share on social media