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- research-articleJune 1988
A New Bit-Serial Systolic Multiplier Over GF(2/sup m/)
IEEE Transactions on Computers (ITCO), Volume 37, Issue 6June 1988, Pages 749–751https://doi.org/10.1109/12.2216A bit-serial systolic array has been developed to computer multiplications over GF(2/sup m/). In contrast to a previously designed systolic multiplier, this algorithm allows the input elements to center a linear systolic array in the same order, and the ...
- research-articleJune 1988
A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases
IEEE Transactions on Computers (ITCO), Volume 37, Issue 6June 1988, Pages 735–739https://doi.org/10.1109/12.2212Three different finite-field multipliers are presented: (1) a dual-basis multiplier due to E.R. Berlekamp (1982); the Massey-Omura normal basis multiplier; and (3) the Scott-Tavares-Peppard standard basis multiplier. These algorithms are chosen because ...
- research-articleJune 1988
Abstract pecification of Synchronous Data Types for VLSI and Proving the Correctness of Systolic Network Implementations
IEEE Transactions on Computers (ITCO), Volume 37, Issue 6June 1988, Pages 710–720https://doi.org/10.1109/12.2209A combined methodology is presented for specifying abstract synchronous data types and proving the correctness of systolic network implementations. It is shown that an extension of the Parnas trace method of specifying software modules containing ...