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- research-articleNovember 2021
The Strong Scaling Advantage of FPGAs in HPC for N-body Simulations
ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 15, Issue 1Article No.: 10, Pages 1–30https://doi.org/10.1145/3491235N-body methods are one of the essential algorithmic building blocks of high-performance and parallel computing. Previous research has shown promising performance for implementing n-body simulations with pairwise force calculations on FPGAs. However, to ...
- research-articleNovember 2020
ApproxFPGAs: embracing ASIC-based approximate arithmetic components for FPGA-based systems
DAC '20: Proceedings of the 57th ACM/EDAC/IEEE Design Automation ConferenceArticle No.: 118, Pages 1–6There has been abundant research on the development of Approximate Circuits (ACs) for ASICs. However, previous studies have illustrated that ASIC-based ACs offer asymmetrical gains in FPGA-based accelerators. Therefore, an AC that might be pareto-...
- research-articleApril 2001
Design of synchronous and asynchronous variable-latency pipelined multipliers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 9, Issue 2Pages 365–376https://doi.org/10.1109/92.924058This paper presents a novel variable-latency multiplier architecture, suitable for implementation as a self-timed multiplier core or as a fully synchronous multicycle multiplier core. The architecture combines a second-order Booth algorithm with a split ...
- ArticleMarch 1995
Accumulator-based BIST approach for stuck-open and delay fault testing
In this paper a novel accumulator-based Built-In Self Test (BIST) method for complete two-pattern test generation is presented. Complete two-pattern testing has been proposed for stuck-open and delay testing. The proposed scheme is very attractive for a ...