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- posterFebruary 2015
An FPGA Implementation of a Timing-Error Tolerant Discrete Cosine Transform (Abstract Only)
FPGA '15: Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysPage 266https://doi.org/10.1145/2684746.2689113We present a Discrete Cosine Transform (DCT) unit embedded with Error Detection Sequential (EDS) and Dynamic Voltage Scaling (DVS) circuits to speculatively monitor its noncritical datapaths. This monitoring strategy requires no buffer insertions with ...
- ArticleMay 2013
Demo: A Node's Life -- Increasing WSN Lifetime by Dynamic Voltage Scaling
DCOSS '13: Proceedings of the 2013 IEEE International Conference on Distributed Computing in Sensor SystemsPages 472–473https://doi.org/10.1109/DCOSS.2013.81In mobile applications, like wireless sensor networks, it is often inevitable to use a location-independent source of energy. Wherever the batteries capacity or inefficient energy harvesting limits the lifetime, other solutions have to be implemented to ...
- ArticleMay 2013
A Node's Life: Increasing WSN Lifetime by Dynamic Voltage Scaling
DCOSS '13: Proceedings of the 2013 IEEE International Conference on Distributed Computing in Sensor SystemsPages 241–248https://doi.org/10.1109/DCOSS.2013.39In mobile applications, like wireless sensor networks, it is often inevitable to use a location-independent source of energy. Wherever the batteries capacity or inefficient energy harvesting limits the lifetime, other solutions have to be implemented to ...
- research-articleOctober 2011
Energy-efficient fixed-priority scheduling for real-time systems based on threshold work-demand analysis
CODES+ISSS '11: Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesisPages 159–168https://doi.org/10.1145/2039370.2039397In this paper, we study the problem of reducing the energy consumption for hard real-time systems based on fixed-priority (FP) scheme. To balance the static and dynamic energy consumption, the concept of critical speed was proposed in previous research. ...
- research-articleAugust 2011
A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems
ISLPED '11: Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and designPages 391–396This paper introduces a design scheme that improves Energy-Delay Product (EDP) in conventional Dynamic Voltage Scaling (DVS) systems by exploiting timing margins. To achieve this scheme, we designed a high-speed Critical Path Monitor composed of several ...
- research-articleAugust 2010
Temperature- and energy-constrained scheduling in multitasking systems: a model checking approach
ISLPED '10: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and designPages 85–90https://doi.org/10.1145/1840845.1840863The ongoing scaling of semiconductor technology is causing severe increase of on-chip power density and temperature in microprocessors. This has raised urgent requirement for both power and thermal management during each level of system design. In this ...
- research-articleJune 2009
Adagio: making DVS practical for complex HPC applications
- Barry Rountree,
- David K. Lownenthal,
- Bronis R. de Supinski,
- Martin Schulz,
- Vincent W. Freeh,
- Tyler Bletsch
ICS '09: Proceedings of the 23rd international conference on SupercomputingPages 460–469https://doi.org/10.1145/1542275.1542340Power and energy are first-order design constraints in high performance computing. Current research using dynamic voltage scaling (DVS) relies on trading increased execution time for energy savings, which is unacceptable for most high performance ...
- research-articleMay 2008
Compiler-directed frequency and voltage scaling for a multiple clock domain microarchitecture
CF '08: Proceedings of the 5th conference on Computing frontiersPages 209–218https://doi.org/10.1145/1366230.1366267Multiple Clock Domain processors provide an attractive solution to the increasingly challenging problems of clock distribution and power dissipation. They allow their chips to be partitioned into different clock domains, and each domain's frequency (...