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- research-articleNovember 2007
The design of high-performance dynamic asynchronous pipelines: high-capacity style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 15, Issue 11November 2007, Pages 1270–1283https://doi.org/10.1109/TVLSI.2007.902206This paper introduces a high-throughput asynchronous pipeline style, called high-capacity (HC) pipelines, targeted to datapaths that use dynamic logic. This approach includes a novel highly-concurrent handshake protocol, with fewer synchronization ...
- research-articleNovember 2007
The design of high-performance dynamic asynchronous pipelines: lookahead style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 15, Issue 11November 2007, Pages 1256–1269https://doi.org/10.1109/TVLSI.2007.902205A new class of asynchronous pipelines is proposed, called lookahead pipelines (LP), which use dynamic logic and are capable of delivering multi-gigahertz throughputs. Since they are asynchronous, these pipelines avoid problems related to high-speed ...
- research-articleJune 2007
MOUSETRAP: high-speed transition-signaling asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 15, Issue 6June 2007, Pages 684–698https://doi.org/10.1109/TVLSI.2007.898732An asynchronous pipeline style is introduced for high-speed applications, called MOUSETRAP. The pipeline uses standard transparent latches and static logic in its datapath, and small latch controllers consisting of only a single gate per pipeline stage. ...
- ArticleSeptember 2001
MOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines
ICCD '01: Proceedings of the International Conference on Computer Design: VLSI in Computers & ProcessorsSeptember 2001, Page 9Abstract: A new asynchronous pipeline design is introduced for high-speed applications. The pipeline uses simple transparent latches in its datapath, and small latch controllers consisting of only a single gate per pipeline stage. This simple stage ...