research-article

MOUSETRAP: high-speed transition-signaling asynchronous pipelines

Authors:

Steven M. NowickAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 15, Issue 6

Pages 684 - 698

https://doi.org/10.1109/TVLSI.2007.898732

Published: 01 June 2007 Publication History

Abstract

An asynchronous pipeline style is introduced for high-speed applications, called MOUSETRAP. The pipeline uses standard transparent latches and static logic in its datapath, and small latch controllers consisting of only a single gate per pipeline stage. This simple structure is combined with an efficient and highly-concurrent event-driven protocol between adjacent stages. Post-layout SPICE simulations of a ten-stage pipeline with a 4-bit wide datapath indicate throughputs of 2.1-2.4 GHz in a 0.18-µm TSMC CMOS process. Similar results were obtained when the datapath width was extended to 16 bits. This performance is competitive even with that of wave pipelines [40], [19] without the accompanying problems of complex timing and much design effort. Additionally, the new pipeline gracefully and robustly adapts to variable speed environments. The pipeline stages are extended to fork and join structures, to handle more complex system architectures.

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Cited By

Han SJang MKang JAamodt TJerger NSwift M(2023)ShakeFlow: Functional Hardware Description with Latency-Insensitive Interface CombinatorsProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 210.1145/3575693.3575701(702-717)Online publication date: 27-Jan-2023
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Dashkin RManohar R(2022)General Approach to Asynchronous Circuits Simulation Using Synchronous FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.313154641:10(3452-3465)Online publication date: 1-Oct-2022
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Index Terms

MOUSETRAP: high-speed transition-signaling asynchronous pipelines
1. Hardware
  1. Hardware validation
  2. Integrated circuits

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cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 15, Issue 6

June 2007

117 pages

ISSN:1063-8210

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Copyright © 2007.

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IEEE Educational Activities Department

United States

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Published: 01 June 2007

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Cited By

Han SJang MKang JAamodt TJerger NSwift M(2023)ShakeFlow: Functional Hardware Description with Latency-Insensitive Interface CombinatorsProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 210.1145/3575693.3575701(702-717)Online publication date: 27-Jan-2023
https://dl.acm.org/doi/10.1145/3575693.3575701
Ayes AFriedman E(2023)Linear Clock Tree Topology for Dynamic Source Synchronous and Fully Synchronous 3-D InterfacesIntegration, the VLSI Journal10.1016/j.vlsi.2023.10206693:COnline publication date: 1-Nov-2023
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Dashkin RManohar R(2022)General Approach to Asynchronous Circuits Simulation Using Synchronous FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.313154641:10(3452-3465)Online publication date: 1-Oct-2022
https://dl.acm.org/doi/10.1109/TCAD.2021.3131546
Heo JKim T(2021)Reusable Delay Path Synthesis for Lightening Asynchronous Pipeline ControllerIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.307338329:7(1437-1450)Online publication date: 1-Jul-2021
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Kavitha RKhajamastan AAkhilesh YVenkataramani B(2020)High-performance asynchronous pipeline using embedded delay elementMicroprocessors & Microsystems10.1016/j.micpro.2019.10295573:COnline publication date: 1-Mar-2020
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