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Logical effort: designing fast CMOS circuitsJanuary 1999
- Authors:
- Ivan Sutherland,
- Bob Sproull,
- David Harris
Abstract
No abstract available.
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Index Terms
- Logical effort: designing fast CMOS circuits
Reviews
Andrew Donald Booth
A design philosophy and method for designing integrated circuits so as to satisfy specified criteria—principally maximum speed—are explained in this exciting and useful text. The first two chapters introduce the method and illustrate its virtues by giving three typical examples of its use. This is followed by a more formal derivation of the method. Next, the authors discuss various types of gate element and how the design method is validated. An important problem in massive gate arrays is the relationship between the driving capacity of a single gate element and the speed of operation of a system driven by that element. The authors examine all of this in detail, with reference to a number of practically useful devices. Finally, they provide an impartial analysis of what has been achieved and a comparison with other techniques. The book ends with a definition of symbols used, a table of useful parameters, and solutions to odd-numbered examples. There is a good bibliography and a comprehensive index. Each chapter contains both worked examples and problems for students. A useful idea is borrowed from Knuth: each example bears a number that indicates its difficulty, and the authors relate this to how long they expect it will take to solve the problem. Practicing engineers and advanced students will profit from this most readable and useful text. I t is eminently suitable for instructional use.
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