Article

Design of a cell library for asynchronous microengines

Authors:

Erik BrunvandAuthors Info & Claims

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

Pages 385 - 389

https://doi.org/10.1145/1057661.1057753

Published: 17 April 2005 Publication History

Abstract

Asynchronous microengines are an attractive alternative to globally synchronous systems for the realization of high performance programmable controllers. However, because of the specific demands of asynchronous signaling, it is not always easy to use existing standard cell libraries to implement asynchronous microengines. In this paper we present the design and evaluation of a CMOS cell set that augments a generic cell library with cells specific to the design of asynchronous microengines. These cells encapsulate behavior and timing information critical to the implementation of asynchronous microengine controllers. These special purpose cells result in higher performance circuits, and in a significant reduction in design time over a generic library. To validate the library, the control path of a popular asynchronous controller benchmark has been designed and fabricated through MOSIS.

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Cited By

Moreira MOliveira BPontes JCalazans N(2011)A 65nm standard cell set and flow dedicated to automated asynchronous circuits design2011 IEEE International SOC Conference10.1109/SOCC.2011.6085103(99-104)Online publication date: Sep-2011
https://doi.org/10.1109/SOCC.2011.6085103

Index Terms

Design of a cell library for asynchronous microengines
1. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific instruction set processors
2. Software and its engineering
  1. Software notations and tools
    1. General programming languages
      1. Language features
        Control structures

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Published In

cover image ACM Conferences

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

April 2005

518 pages

ISBN:1595930574

DOI:10.1145/1057661

General Chair:
John Lach
University of Virginia
,
Program Chairs:
Gang Qu
University of Maryland, College Park
,
Yehea Ismail
Northwestern University

Copyright © 2005 ACM.

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New York, NY, United States

Publication History

Published: 17 April 2005

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GLSVLSI05

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GLSVLSI05: Great Lakes Symposium on VLSI 2005

April 17 - 19, 2005

Illinois, Chicago, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Moreira MOliveira BPontes JCalazans N(2011)A 65nm standard cell set and flow dedicated to automated asynchronous circuits design2011 IEEE International SOC Conference10.1109/SOCC.2011.6085103(99-104)Online publication date: Sep-2011
https://doi.org/10.1109/SOCC.2011.6085103

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