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The Design of an Asynchronous MIPS R3000 Microprocessor

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Uri CummingsAuthors Info & Claims

ARVLSI '97: Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)

Page 164

Published: 15 September 1997 Publication History

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Abstract

The design of an asynchronous clone of a MIPS R3000 microprocessor is presented. In 0.6 micron CMOS, we expect performance close to 280 MIPS, for a power consumption of 7 Watts. The paper describes the structure of a high- performance asynchronous pipeline, in particular precise exceptions, pipelined caches, arithmetic, and registers, and the circuit techniques developed to achieve high frequency.

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Cited By

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Raji MGhavami B(2018)Redressing fork constraints in nanoscale quasi-delay-insensitive asynchronous pipelinesThe Journal of Supercomputing10.1007/s11227-017-2056-074:8(3820-3840)Online publication date: 1-Aug-2018
https://dl.acm.org/doi/10.1007/s11227-017-2056-0
Bhadra DStevens K(2017)Design of a low power, relative timing based asynchronous MSP430 microprocessorProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130571(794-799)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130571
Wu GChu CFanucci LTeich J(2016)Simultaneous slack matching, gate sizing and repeater insertion for asynchronous circuitsProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972051(1042-1047)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2972051
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Index Terms

The Design of an Asynchronous MIPS R3000 Microprocessor
1. Hardware
  1. Integrated circuits

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ARVLSI '97: Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)

September 1997

ISBN:0818679131

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IEEE Computer Society

United States

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Published: 15 September 1997

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Raji MGhavami B(2018)Redressing fork constraints in nanoscale quasi-delay-insensitive asynchronous pipelinesThe Journal of Supercomputing10.1007/s11227-017-2056-074:8(3820-3840)Online publication date: 1-Aug-2018
https://dl.acm.org/doi/10.1007/s11227-017-2056-0
Bhadra DStevens K(2017)Design of a low power, relative timing based asynchronous MSP430 microprocessorProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130571(794-799)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130571
Wu GChu CFanucci LTeich J(2016)Simultaneous slack matching, gate sizing and repeater insertion for asynchronous circuitsProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972051(1042-1047)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2972051
Wang ZHe XSechen C(2015)A New Approach for Gate-Level Delay-Insensitive Asynchronous LogicCircuits, Systems, and Signal Processing10.5555/2765121.276513734:5(1431-1459)Online publication date: 1-May-2015
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Longfield SNkounkou BManohar RTate R(2015)Preventing glitches and short circuits in high-level self-timed chip specificationsACM SIGPLAN Notices10.1145/2813885.273796750:6(270-279)Online publication date: 3-Jun-2015
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Casu MMantovani P(2015)A synchronous latency-insensitive RISC for better than worst-case designIntegration, the VLSI Journal10.1016/j.vlsi.2014.01.00348:C(72-82)Online publication date: 1-Jan-2015
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Najibi MBeerel PHenkel J(2013)Slack matching mode-based asynchronous circuits for average-case performanceProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561873(219-225)Online publication date: 18-Nov-2013
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