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(2018). Redressing fork constraints in nanoscale quasi-delay-insensitive asynchronous pipelines. The Journal of Supercomputing. 74:8. (3820-3840). Online publication date: 1-Aug-2018.
Bhadra D and Stevens K. Design of a low power, relative timing based asynchronous MSP430 microprocessor. Proceedings of the Conference on Design, Automation & Test in Europe. (794-799).
Wu G and Chu C. Simultaneous slack matching, gate sizing and repeater insertion for asynchronous circuits. Proceedings of the 2016 Conference on Design, Automation & Test in Europe. (1042-1047).
Longfield S, Nkounkou B, Manohar R and Tate R.
(2015). Preventing glitches and short circuits in high-level self-timed chip specifications. ACM SIGPLAN Notices. 50:6. (270-279). Online publication date: 7-Aug-2015.
Longfield S, Nkounkou B, Manohar R and Tate R. Preventing glitches and short circuits in high-level self-timed chip specifications. Proceedings of the 36th ACM SIGPLAN Conference on Programming Language Design and Implementation. (270-279).
Wang Z, He X and Sechen C.
(2015). A New Approach for Gate-Level Delay-Insensitive Asynchronous Logic. Circuits, Systems, and Signal Processing. 34:5. (1431-1459). Online publication date: 1-May-2015.
Casu M and Mantovani P.
(2015). A synchronous latency-insensitive RISC for better than worst-case design. Integration, the VLSI Journal. 48:C. (72-82). Online publication date: 1-Jan-2015.
Longfield S and Manohar R. Removing concurrency for rapid functional verification. Proceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design. (332-339).
Najibi M and Beerel P. Slack matching mode-based asynchronous circuits for average-case performance. Proceedings of the International Conference on Computer-Aided Design. (219-225).
Sheikh B and Manohar R.
(2011). Energy-Efficient Pipeline Templates for High-Performance Asynchronous Circuits. ACM Journal on Emerging Technologies in Computing Systems. 7:4. (1-26). Online publication date: 1-Dec-2011.
Casu M, Colazzo S and Mantovani P. Coupling latency-insensitivity with variable-latency for better than worst case design. Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI. (163-168).
Taylor S, Edwards D, Plana L and Tarazona D.
(2010). Asynchronous data-driven circuit synthesis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18:7. (1093-1106). Online publication date: 1-Jul-2010.
Carmona J, Cortadella J, Kishinevsky M and Taubin A.
(2009). Elastic circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28:10. (1437-1455). Online publication date: 1-Oct-2009.
Singh M and Nowick S.
(2007). The design of high-performance dynamic asynchronous pipelines. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 15:11. (1270-1283). Online publication date: 1-Nov-2007.
Singh M and Nowick S.
(2007). The design of high-performance dynamic asynchronous pipelines. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 15:11. (1256-1269). Online publication date: 1-Nov-2007.
Chelcea T, Venkataramani G and Goldstein S. Self-resetting latches for asynchronous micro-pipelines. Proceedings of the 44th annual Design Automation Conference. (986-989).
Singh M and Nowick S.
(2007). MOUSETRAP. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 15:6. (684-698). Online publication date: 1-Jun-2007.
Taubin A, Cortadella J, Lavagno L, Kondratyev A and Peeters A.
(2007). Design automation of real-life asynchronous devices and systems. Foundations and Trends in Electronic Design Automation. 2:1. (1-133). Online publication date: 1-Jan-2007.
Lee J, Choi E and Cho K. Design of asynchronous embedded processor with new ternary data encoding scheme. Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation. (395-405).
Peng S and Manohar R. Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology. Proceedings of the 16th ACM Great Lakes symposium on VLSI. (159-164).
Hasasneh N, Bell I and Jesshope C. Scalable and partitionable asynchronous arbiter for micro-threaded chip multiprocessors. Proceedings of the 19th international conference on Architecture of Computing Systems. (252-267).
Reese R, Thornton M and Traver C.
(2005). A Coarse-Grain Phased Logic CPU. IEEE Transactions on Computers. 54:7. (788-799). Online publication date: 1-Jul-2005.
McGee P and Nowick S. A lattice-based framework for the classification and design of asynchronous pipelines. Proceedings of the 42nd annual Design Automation Conference. (491-496).
Peng S, Fang D, Teifel J and Manohar R. Automated synthesis for asynchronous FPGAs. Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays. (163-173).
Ekanayake V, Kelly C and Manohar R.
(2004). An ultra low-power processor for sensor networks. ACM SIGOPS Operating Systems Review. 38:5. (27-36). Online publication date: 1-Dec-2004.
Ekanayake V, Kelly C and Manohar R.
(2004). An ultra low-power processor for sensor networks. ACM SIGARCH Computer Architecture News. 32:5. (27-36). Online publication date: 1-Dec-2004.
Ekanayake V, Kelly C and Manohar R.
(2004). An ultra low-power processor for sensor networks. ACM SIGPLAN Notices. 39:11. (27-36). Online publication date: 1-Nov-2004.
Ekanayake V, Kelly C and Manohar R. An ultra low-power processor for sensor networks. Proceedings of the 11th international conference on Architectural support for programming languages and operating systems. (27-36).
Fazel K, Li L, Thornton M, Reese R and Traver C. Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion. Proceedings of the 14th ACM Great Lakes symposium on VLSI. (413-416).
Teifel J and Manohar R. Highly pipelined asynchronous FPGAs. Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays. (133-142).
Melhem R, Mossé D and Elnozahy E.
(2004). The Interplay of Power Management and Fault Recovery in Real-Time Systems. IEEE Transactions on Computers. 53:2. (217-231). Online publication date: 1-Feb-2004.
Talpes E and Marculescu D. A critical analysis of application-adaptive multiple clock processors. Proceedings of the 2003 international symposium on Low power electronics and design. (278-281).
Wong C and Martin A. High-level synthesis of asynchronous systems by data-driven decomposition. Proceedings of the 40th annual Design Automation Conference. (508-513).
Pénzes P, Nyström M and Martin A. Transistor sizing of energy-delay--efficient circuits. Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems. (126-133).
Manohar R. Scalable formal design methods for asynchronous VLSI. Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages. (245-246).
Kim S and Beerel P. Pipeline optimization for asynchronous circuits. Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design. (296-302).
Brunvand E, Nowick S and Yun K. Practical advances in asynchronous design and in asynchronous/synchronous interfaces. Proceedings of the 36th annual ACM/IEEE Design Automation Conference. (104-109).