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An ultra low-power processor for sensor networks

Published: 07 October 2004 Publication History

Abstract

We present a novel processor architecture designed specifically for use in low-power wireless sensor-network nodes. Our sensor network asynchronous processor (SNAP/LE) is based on an asynchronous data-driven 16-bit RISC core with an extremely low-power idle state, and a wakeup response latency on the order of tens of nanoseconds. The processor instruction set is optimized for sensor-network applications, with support for event scheduling, pseudo-random number generation, bitfield operations, and radio/sensor interfaces. SNAP/LE has a hardware event queue and event coprocessors, which allow the processor to avoid the overhead of operating system software (such as task schedulers and external interrupt servicing), while still providing a straightforward programming interface to the designer. The processor can meet performance levels required for data monitoring applications while executing instructions with tens of picojoules of energy.We evaluate the energy consumption of SNAP/LE with several applications representative of the workload found in data-gathering wireless sensor networks. We compare our architecture and software against existing platforms for sensor networks, quantifying both the software and hardware benefits of our approach.

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Published In

cover image ACM SIGARCH Computer Architecture News
ACM SIGARCH Computer Architecture News  Volume 32, Issue 5
ASPLOS 2004
December 2004
283 pages
ISSN:0163-5964
DOI:10.1145/1037947
Issue’s Table of Contents
  • cover image ACM Conferences
    ASPLOS XI: Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
    October 2004
    296 pages
    ISBN:1581138040
    DOI:10.1145/1024393
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 07 October 2004
Published in SIGARCH Volume 32, Issue 5

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Author Tags

  1. asynchronous
  2. event-driven
  3. low-energy
  4. picojoule computing
  5. sensor network processor
  6. sensor networks
  7. wireless

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  • (2015)Accelerating asynchronous programs through event sneak peekACM SIGARCH Computer Architecture News10.1145/2872887.275037343:3S(642-654)Online publication date: 13-Jun-2015
  • (2015)Accelerating asynchronous programs through event sneak peekProceedings of the 42nd Annual International Symposium on Computer Architecture10.1145/2749469.2750373(642-654)Online publication date: 13-Jun-2015
  • (2011)Power/energy estimator for designing WSN nodes with ambient energy harvesting featureEURASIP Journal on Embedded Systems10.1155/2011/2423862011(1-17)Online publication date: 1-Jan-2011
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