research-article

The Message-Driven Processor: A Multicomputer Processing Node with Efficient Mechanisms

Authors:

William J. Dally,

J. A. Stuart Fiske,

Richard A. Lethin,

Michael D. Noakes,

Roy E. Davison,

Gregory A. FylerAuthors Info & Claims

IEEE Micro, Volume 12, Issue 2

Pages 23 - 39

https://doi.org/10.1109/40.127581

Published: 01 March 1992 Publication History

Abstract

The message-driven processor (MDP), a 36-b, 1.1-million transistor, VLSI microcomputer, specialized to operate efficiently in a multicomputer, is described. The MDP chip includes a processor, a 4096-word by 36-b memory, and a network port. An on-chip memory controller with error checking and correction (ECC) permits local memory to be expanded to one million words by adding external DRAM chips. The MDP incorporates primitive mechanisms for communication, synchronization, and naming which support most proposed parallel programming models. The MDP system architecture, instruction set architecture, network architecture, implementation, and software are discussed.

References

[1]

1. W.J. Dally, D.S. Wills, and R. Lethin, "Mechanisms for Parallel Computing," Proc. NATO Advanced Study Institute on Parallel Computing on Distributed Memory Multiprocessors, Springer-Verlag, New York, 1991.

[2]

2. A. Gottlieb et al., "The NYU Ultracomputer-Designing a MIMD Shared Memory Parallel Computer," IEEE Trans. Computers, Vol. C-32, No. 2, Feb. 1983, pp. 175-189.

[3]

3. W.D. Hillis and G.L. Steele, "Data Parallel Algorithms," Comm. of the ACM, Vol. 29, No. 12, 1986, pp. 1170-1183.

Digital Library

[4]

4. A. H. Veen, "Dataflow Machine Architecture," ACM Computing Surveys, Vol. 18, No. 4, Dec. 1986, pp. 365-396.

Digital Library

[5]

5. G. Agha, "Actors: A Model of Concurrent Computation in Distributed Systems," Tech. Report 844, Artificial Intelligence Laboratory, Massachusetts Inst. of Technology, Cambridge, Mass., 1985.

[6]

6. W.C. Athas and C.L. Seitz, "Multicomputers: Message-Passing Concurrent Computers," Computer, Vol. 21, No. 8, Aug. 1988, pp. 9-24.

Digital Library

[7]

7. W.J. Dally, "Performance Analysis of k-ary n-cube Interconnection Networks," IEEE Trans. Computers, Vol. 39, No. 6, June 1990, pp. 775-785.

Digital Library

[8]

8. R. Arlauskas, "iPSC/2 System: A Second-Generation Hypercube," Proc. Third Conf. Hypercube Concurrent Computers and Applications, Assn. for Computing Machinery, New York, 1988, pp. 33-36.

[9]

9. J.F. Palmer, "The Ncube Family of Parallel Supercomputers," Proc. IEEE Int'l Conf. Computer Design, IEEE CS Press, Los Alamitos, Calif., 1986, p. 107.

[10]

10. Series 2010 Product Description, Ametek Computer Research Division, Monrovia, Calif., 1987.

[11]

11. "Butterfly Parallel Processor Overview," BBN Report 6148, Bolt, Beranek and Newman Advanced Computers, Inc., Cambridge, Mass., Mar. 1986.

[12]

12. W.C. Brantley, K.P. McAuliffe, and J. Weiss, "RP3 Processor-Memory Element," IEEE Trans. Computers, Vol. C-34, No. 10, Sept. 1985, pp. 782-789.

[13]

13. I. Barron et al., "Transputer Does Five or More MIPS Even When Not Used in Parallel," Electronics, Nov. 1983, pp. 109-115.

[14]

14. C. Lutz et al., "Design of the Mosaic Element," Proc. MIT Conf. Advanced Research in VLSI, Artech Books, Dedham, Mass., 1984, pp. 1-10.

[15]

15. S. Borkar et al., " iWarp: An Integrated Solution to High-Speed Parallel Computing," Proc. Supercomputing Conf., IEEE CS Press, Nov. 1988, pp. 330-338.

[16]

16. W.J. Dally and C.L. Seitz, "The Torus Routing Chip," Distributed Computing, Vol. 1, 1986, pp. 187-196.

[17]

17. W.J. Dally and P. Song, "Design of a Self-Timed VLSI Multicomputer Communication Controller," Proc. Int'l Conf. Computer Design, pp. 230-234. IEEE CS Press, Oct. 1987.

[18]

18. PC. Yew, N.F. Tzeng, and D.H. Lawrie, "Distributing Hot-Spot Addressing in Large-Scale Multiprocessors," IEEE Trans. Computers, Vol. C-36, No. 4, Apr. 1987, pp. 388-395.

[19]

19. W.J. Dally et al., "Architecture of a Message-Driven Processor," Proc. 14th Int'l Symp. Computer Architecture, IEEE CS Press, June 1987, pp. 189-205.

[20]

20. P.R. Nuth, "Router Protocol," internal memo23, MIT Concurrent VLSI Architecture Group, 1990.

[21]

21. W.J. Dally and C.L. Seitz, "Deadlock-Free Message Routing in Multiprocessor Interconnection Networks," IEEE Trans. Computers, Vol. C-36, No. 5, May 1987, pp. 547-553.

[22]

22. M. Noakes and W.J. Dally, "System Design of the J-Machine," Proc. Sixth MIT Conf. Advanced Research in VLSI, W.J. Dally, ed., MIT Press, Cambridge, Mass, 1990, pp. 179-194.

Digital Library

[23]

23. W. Horwat, "Concurrent Smalltalk on the Message-Driven Processor," master's thesis, MIT, May 1989.

[24]

24. R.S. Nikhil, ID Version 88.1 Reference Manual, Tech. Report 284, Computation Structure Group, MIT, 1988.

[25]

25. D.E. Culler et al., "Fine-Grain Parallelism with Minimal Hardware Support: A Compiler-Controlled Threaded Abstract Machine," Proc. Fourth Int'l Conf. Architectural Support for Programming Languages and Operating Systems, 1991, pp. 164-175.

[26]

26. E. Spertus and W.J. Dally, "Experiments with Dataflow on a General-Purpose Parallel Computer," Proc. Int'l Conf. Parallel Processing, Aug. 1991, pp. II-231-II-235.

Cited By

Dysart TKogge PDeneroff MBovell EBriggs PBrockman JJacobsen KJuan YKuntz SLethin RMcMahon JPawar CPerrigo MRucker SRuttenberg JRuttenberg MStein S(2016)Highly scalable near memory processing with migrating threads on the emu system architectureProceedings of the Sixth Workshop on Irregular Applications: Architectures and Algorithms10.5555/3018843.3018845(2-9)Online publication date: 13-Nov-2016
https://dl.acm.org/doi/10.5555/3018843.3018845
Cui HWang LFan DFeng X(2010)Landing stencil code on Godson-TJournal of Computer Science and Technology10.5555/1946459.194647925:4(886-894)Online publication date: 1-Jul-2010
https://dl.acm.org/doi/10.5555/1946459.1946479
Vallejo EBeivide RCristal AHarris TVallejo FUnsal OValero M(2010)Architectural Support for Fair Reader-Writer LockingProceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2010.12(275-286)Online publication date: 4-Dec-2010
https://dl.acm.org/doi/10.1109/MICRO.2010.12
Show More Cited By

Recommendations

Message-Driven Processor Architecture, Version 11
Architecture of a message-driven processor
ISCA '87: Proceedings of the 14th annual international symposium on Computer architecture

We propose a machine architecture for a high-performance processing node for a message-passing, MIMD concurrent computer. The principal mechanisms for attaining this goal are the direct execution and buffering of messages and a memory-based architecture ...
A uGNI-based Asynchronous Message-driven Runtime System for Cray Supercomputers with Gemini Interconnect
IPDPS '12: Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium

Gemini, the network for the new Cray XE/XK systems, features low latency, high bandwidth and strong scalability. Its hardware support for remote direct memory access enables efficient implementation of the global address space programming languages. ...

Comments

Information & Contributors

Information

Published In

cover image IEEE Micro

IEEE Micro Volume 12, Issue 2

March 1992

89 pages

ISSN:0272-1732

Issue’s Table of Contents

Copyright © Copyright © 1992 IEEE. All Rights Reserved.

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 March 1992

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

70
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 26 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

Dysart TKogge PDeneroff MBovell EBriggs PBrockman JJacobsen KJuan YKuntz SLethin RMcMahon JPawar CPerrigo MRucker SRuttenberg JRuttenberg MStein S(2016)Highly scalable near memory processing with migrating threads on the emu system architectureProceedings of the Sixth Workshop on Irregular Applications: Architectures and Algorithms10.5555/3018843.3018845(2-9)Online publication date: 13-Nov-2016
https://dl.acm.org/doi/10.5555/3018843.3018845
Cui HWang LFan DFeng X(2010)Landing stencil code on Godson-TJournal of Computer Science and Technology10.5555/1946459.194647925:4(886-894)Online publication date: 1-Jul-2010
https://dl.acm.org/doi/10.5555/1946459.1946479
Vallejo EBeivide RCristal AHarris TVallejo FUnsal OValero M(2010)Architectural Support for Fair Reader-Writer LockingProceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2010.12(275-286)Online publication date: 4-Dec-2010
https://dl.acm.org/doi/10.1109/MICRO.2010.12
Owens JDally WHo RJayasimha DKeckler SPeh L(2007)Research Challenges for On-Chip Interconnection NetworksIEEE Micro10.5555/1320302.132084127:5(96-108)Online publication date: 1-Sep-2007
https://dl.acm.org/doi/10.5555/1320302.1320841
Butts M(2007)Synchronization through Communication in a Massively Parallel Processor ArrayIEEE Micro10.5555/1320302.132083527:5(32-40)Online publication date: 1-Sep-2007
https://dl.acm.org/doi/10.5555/1320302.1320835
Zhu WSreedhar VHu ZGao G(2007)Synchronization state bufferACM SIGARCH Computer Architecture News10.1145/1273440.125066835:2(35-45)Online publication date: 9-Jun-2007
https://dl.acm.org/doi/10.1145/1273440.1250668
Zhu WSreedhar VHu ZGao GTullsen DCalder B(2007)Synchronization state bufferProceedings of the 34th annual international symposium on Computer architecture10.1145/1250662.1250668(35-45)Online publication date: 9-Jun-2007
https://dl.acm.org/doi/10.1145/1250662.1250668
Brockman JThoziyoor SKuntz SKogge PCarter JZhang L(2004)A low cost, multithreaded processing-in-memory systemProceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture10.1145/1054943.1054946(16-22)Online publication date: 20-Jun-2004
https://dl.acm.org/doi/10.1145/1054943.1054946
Ekanayake VKelly CManohar R(2004)An ultra low-power processor for sensor networksACM SIGOPS Operating Systems Review10.1145/1037949.102439738:5(27-36)Online publication date: 7-Oct-2004
https://dl.acm.org/doi/10.1145/1037949.1024397
Ekanayake VKelly CManohar R(2004)An ultra low-power processor for sensor networksACM SIGARCH Computer Architecture News10.1145/1037947.102439732:5(27-36)Online publication date: 7-Oct-2004
https://dl.acm.org/doi/10.1145/1037947.1024397
Show More Cited By

View Options

View options

Media

Figures

Other

Tables

View Issue’s Table of Contents