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Architecture of a message-driven processor

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S. WillsAuthors Info & Claims

ISCA '87: Proceedings of the 14th annual international symposium on Computer architecture

Pages 189 - 196

https://doi.org/10.1145/30350.30372

Published: 01 June 1987 Publication History

Abstract

We propose a machine architecture for a high-performance processing node for a message-passing, MIMD concurrent computer. The principal mechanisms for attaining this goal are the direct execution and buffering of messages and a memory-based architecture that permits very fast context switches. Our architecture also includes a novel memory organization that permits both indexed and associative accesses and that incorporates an instruction buffer and message queue. Simulation results suggest that this architecture reduces message reception overhead by more than an order of magnitude.

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Architecture of a message-driven processor

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cover image ACM Conferences

ISCA '87: Proceedings of the 14th annual international symposium on Computer architecture

June 1987

321 pages

ISBN:0818607769

DOI:10.1145/30350

Editor:
D. St. Clair

Copyright © 1987 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 1987

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ISCA87: The 14th Annual International Symposium on Computer Architecture

June 2 - 5, 1987

Pennsylvania, Pittsburgh, USA

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Overall Acceptance Rate 543 of 3,203 submissions, 17%

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Fioretto FYeoh W(2018)AI buzzwords explainedAI Matters10.1145/3175502.31755063:4(8-13)Online publication date: 16-Feb-2018
https://dl.acm.org/doi/10.1145/3175502.3175506
Tsai PChen CSanchez DOskin MInoue K(2018)Adaptive scheduling for systems with asymmetric memory hierarchiesProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00058(641-654)Online publication date: 20-Oct-2018
https://dl.acm.org/doi/10.1109/MICRO.2018.00058
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