It is a common belief that computer performance growth is over 50% annually, or that performance doubles every 18-20 months. By analyzing publicly available results from the SPEC integer (CINT) benchmark suites, we conclude that this was true between ...

The IBM™ S/390™ architecture is a complex architecture, which has grown over a long period of time. Typical implementations use microcode to cope with the more complex instructions and facilities of S/390. Current IBM S/390 processors even ...

We present a compiler and microarchitecture assisted framework for dynamic energy monitoring by a program. The programs will perform an ealloc (The operating system will support energy allocation through a program level utility ealloc similar to the ...

Simultaneous Speculation Scheduling (S³) is a combined compiler and architecture technique to control multiple path execution. It can be used for dual path branch speculation in case of unpredictable branches and for multiple path speculative execution ...

Software pipelining can generate efficient schedules for loop by overlapping the execution of operations from different iterations in order to exploit maximum Instruction Level Parallelism (ILP). Code optimization can decrease total number of ...

The architecture described in the following articel is a direct successor of µ-EP-1 (cf. [1]) and was developed by the author and Robert Linden (Universität Bonn, FB Informatik). NICE is a 32-bit processor, utilizing a fixed instruction ...

Instruction traces are useful tools for studying many aspects of computer systems, but they are difficult to gather without perturbing the systems being traced. In the past, researchers have collected instruction traces through various techniques, ...

This work presents an academic RISC processor architecture, named DMN-6 that executes every instruction in the datapath. It concentrates all the movement, branch and alu instructions in the arithmetic-logic unit. The idea is to normalize the control ...

This paper focuses on extending the memory subsystem by integrating a prefetch buffer mechanism. Prefetching allows high-level application knowledge to increase memory performance, which is currently constraining the performance of most system. While ...

This article describes a very simple but quite powerful 32-bit architecture ideally suited for experimental and educational purposes in computer architecture design. It employs a very orthogonal instruction set in conjunction with 16 general purpose ...

The model we have developed at Université de Genève allows one to handle irregular data in parallel processing. It achieves much smoother data-driven parallel processing allowing far less discontinuities of the well-known pipeline "bubbles"...

The Counterflow Pipeline Processor, or CFPP, is a unique form of pipelined RISC architecture whose goal is to obtain regular and modular performance from a bi-directional pipeline. In this pipeline, instructions and results move in opposite directions ...

Acquiring extremely dependable results from computers requires attention to all of the stages from program and machine design through execution of the program. One of the smaller, but still important, stages is that of verifying that the sequence of ...