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Microarchitecture of HaL's CPU
COMPCON '95: Proceedings of the 40th IEEE Computer Society International ConferenceThe HaL PM1 CPU is the first implementation of the 64-bit SPARC Version 9 instruction set architecture. The processor utilizes superscalar instruction issue, register renaming, and a dataflow model of execution. Instructions can complete out-of-order ...
Threaded multiple path execution
ISCA '98: Proceedings of the 25th annual international symposium on Computer architectureThis paper presents Threaded Multi-Path Execution (TME), which exploits existing hardware on a Simultaneous Multi-threading (SMT) processor to speculatively execute multiple paths of execution. When there are fewer threads in an SMT processor than ...
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