Article

Kestrel: Design of an 8-bit SIMD Parallel Processor

Authors:

David M. Dahle,

Jeffrey D. Hirschberg,

Hansjoerg Keller,

Douglas H. Williams,

Richard HugheyAuthors Info & Claims

ARVLSI '97: Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)

Page 145

Published: 15 September 1997 Publication History

Abstract

Kestrel is a high-performance programmable parallel co-processor. Its design is the result of examination and reexamination of algorithmic, architectural, packaging, and silicon design issues, and the interrelations between them. The final system features a linear array of 8-bit processing elements, each with local memory, an arithmetic logic unit (ALU), a multiplier, and other functional units. Sixty-four Kestrel processing elements fit in a 1.4 million transistor, 60 mm^2, 0.5 micron CMOS chip with just 84 pins. The planned single-board, 8-chip system will, for some applications, provide supercomputer performance at a fraction of the cost. This paper surveys four of our applications (sequence analysis, neural networks, image compression, and floating-point arithmetic), and discusses the philosophy behind many of the design decisions. We present the processing element and system architectures, emphasizing the ALU and comparator's compact instruction encoding and design, the architecture's facility with nested conditionals, and the multiplier's flexibility in performing multiprecision operations. Finally, we discuss the implementation and performance of the Kestrel test chips.

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Cited By

Di Blas ADahle DDiekhans MGrate LHirschberg JKarplus KKeller HKendrick MJ. Mesa-Martinez FPease DRice ESchultz ASpeck DHughey R(2005)The UCSC Kestrel Parallel ProcessorIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2005.1216:1(80-92)Online publication date: 1-Jan-2005
https://dl.acm.org/doi/10.1109/TPDS.2005.12
Di Blas AJagota AHughey R(2005)Optimizing neural networks on SIMD parallel computersParallel Computing10.1016/j.parco.2004.11.00231:1(97-115)Online publication date: 1-Jan-2005
https://dl.acm.org/doi/10.1016/j.parco.2004.11.002

Index Terms

Kestrel: Design of an 8-bit SIMD Parallel Processor
1. Computer systems organization
  1. Dependable and fault-tolerant systems and networks
2. Networks
  1. Network performance evaluation

Index terms have been assigned to the content through auto-classification.

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cover image Guide Proceedings

ARVLSI '97: Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)

September 1997

ISBN:0818679131

Copyright © Copyright (c) 1997 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

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IEEE Computer Society

United States

Publication History

Published: 15 September 1997

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Cited By

Di Blas ADahle DDiekhans MGrate LHirschberg JKarplus KKeller HKendrick MJ. Mesa-Martinez FPease DRice ESchultz ASpeck DHughey R(2005)The UCSC Kestrel Parallel ProcessorIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2005.1216:1(80-92)Online publication date: 1-Jan-2005
https://dl.acm.org/doi/10.1109/TPDS.2005.12
Di Blas AJagota AHughey R(2005)Optimizing neural networks on SIMD parallel computersParallel Computing10.1016/j.parco.2004.11.00231:1(97-115)Online publication date: 1-Jan-2005
https://dl.acm.org/doi/10.1016/j.parco.2004.11.002

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