Article

DAG based library-free technology mapping

Authors:

L. S. Rosa, Jr.,

S. S. Sapatnekar,

A. I. ReisAuthors Info & Claims

GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI

Pages 293 - 298

https://doi.org/10.1145/1228784.1228857

Published: 11 March 2007 Publication History

Abstract

This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through the longest path, considering that each cell network has to obey to a maximum admitted chain. The number of series transistors is computed in a Boolean way, reducing the structural bias. The mapping algorithm is performed on a Directed Acyclic Graph (DAG) description of the circuit. Preliminary results for delay were obtained through SPICE simulations. When compared to the SIS technology mapping, the proposed method shows significant delay reductions, considering circuits mapped with different libraries.

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Cited By

Wuerdig RMaciel VReis RBampi S(2023)LEX - A Cell Switching Arcs Extractor: A Simple SPICE-Input Interface for Electrical Characterization2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI59464.2023.10238671(1-6)Online publication date: 20-Jun-2023
https://doi.org/10.1109/ISVLSI59464.2023.10238671
Kessler HPorto MDa Rosa LCamargo V(2022)Standard Cell and Supergates Designs: An Electrical Comparison on 4-Input Logic Functions2022 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS48785.2022.9937578(1744-1748)Online publication date: 28-May-2022
https://doi.org/10.1109/ISCAS48785.2022.9937578
Conceicao CReis R(2019)Transistor Count Reduction by Gate MergingIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2019.290772266:6(2175-2187)Online publication date: Jun-2019
https://doi.org/10.1109/TCSI.2019.2907722
Show More Cited By

Index Terms

DAG based library-free technology mapping
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
    2. Logic synthesis
      1. Circuit optimization

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Published In

cover image ACM Conferences

GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI

March 2007

626 pages

ISBN:9781595936059

DOI:10.1145/1228784

General Chairs:
Hai Zhou
Northwestern University
,
Enrico Macii
Politecnico di Torino
,
Program Chairs:
Zhiyuan Yan
Lehigh University
,
Yehia Massoud
Rice University

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 11 March 2007

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GLSVLSI07: Great Lakes Symposium on VLSI 2007

March 11 - 13, 2007

Stresa-Lago Maggiore, Italy

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Wuerdig RMaciel VReis RBampi S(2023)LEX - A Cell Switching Arcs Extractor: A Simple SPICE-Input Interface for Electrical Characterization2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI59464.2023.10238671(1-6)Online publication date: 20-Jun-2023
https://doi.org/10.1109/ISVLSI59464.2023.10238671
Kessler HPorto MDa Rosa LCamargo V(2022)Standard Cell and Supergates Designs: An Electrical Comparison on 4-Input Logic Functions2022 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS48785.2022.9937578(1744-1748)Online publication date: 28-May-2022
https://doi.org/10.1109/ISCAS48785.2022.9937578
Conceicao CReis R(2019)Transistor Count Reduction by Gate MergingIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2019.290772266:6(2175-2187)Online publication date: Jun-2019
https://doi.org/10.1109/TCSI.2019.2907722
Matos JCarrabina JReis A(2019)Efficiently Mapping VLSI Circuits With Simple CellsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.281870938:4(692-704)Online publication date: Apr-2019
https://doi.org/10.1109/TCAD.2018.2818709
Possani VReis ARibas RMarques Fda Rosa L(2017)Transistor Count Optimization in IG FinFET Network DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.262945136:9(1483-1496)Online publication date: Sep-2017
https://doi.org/10.1109/TCAD.2016.2629451
Nachtigall MFerreira PMarques F(2017)Simulated Annealing Applied to LUT-Based FPGA Technology Mapping2017 Sixteenth Mexican International Conference on Artificial Intelligence (MICAI)10.1109/MICAI-2017.2017.00012(23-29)Online publication date: Oct-2017
https://doi.org/10.1109/MICAI-2017.2017.00012
De Carvalho MAltieri MPuricelli LButzen PRibas RFabris E(2016)On-silicon validation of a benchmark generation methodology for effectively evaluating combinational cell library design2016 17th Latin-American Test Symposium (LATS)10.1109/LATW.2016.7483353(135-140)Online publication date: Apr-2016
https://doi.org/10.1109/LATW.2016.7483353
Kadiyala SSamanta D(2015)On-the-Fly Mapping for Synthesizing Dynamic Domino Circuits2015 28th International Conference on VLSI Design10.1109/VLSID.2015.83(458-463)Online publication date: Jan-2015
https://doi.org/10.1109/VLSID.2015.83
Matos JRitt MRibas RReis ADavid EOrdonez Mde Azevedo RKinget P(2014)Deriving Reduced Transistor Count Circuits from AIGsProceedings of the 27th Symposium on Integrated Circuits and Systems Design10.1145/2660540.2661008(1-7)Online publication date: 1-Sep-2014
https://dl.acm.org/doi/10.1145/2660540.2661008
Beiu VIbrahim WTache MLiu T(2014)On ultra-low power hybrid NEMS-CMOS14th IEEE International Conference on Nanotechnology10.1109/NANO.2014.6968045(201-206)Online publication date: Aug-2014
https://doi.org/10.1109/NANO.2014.6968045
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