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Wavefront technology mapping

Authors:

Leon Stok,

Mahesh A. Iyer,

Andrew J. SullivanAuthors Info & Claims

DATE '99: Proceedings of the conference on Design, automation and test in Europe

Pages 108 - es

https://doi.org/10.1145/307418.307559

Published: 01 January 1999 Publication History

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References

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Cited By

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Radi GCalvino ADe Micheli G(2024)In Medio Stat Virtus*: Combining Boolean and Pattern Matching2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473889(404-410)Online publication date: 22-Jan-2024
https://doi.org/10.1109/ASP-DAC58780.2024.10473889
Stok L(2017)EDA3.0: Implications to Logic SynthesisAdvanced Logic Synthesis10.1007/978-3-319-67295-3_1(1-20)Online publication date: 16-Nov-2017
https://doi.org/10.1007/978-3-319-67295-3_1
Marques FRosa LRibas RSapatnekar SReis AZhou HMacii EYan ZMassoud Y(2007)DAG based library-free technology mappingProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228857(293-298)Online publication date: 11-Mar-2007
https://dl.acm.org/doi/10.1145/1228784.1228857
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Index Terms

Wavefront technology mapping
1. Hardware
  1. Integrated circuits
    1. Logic circuits
2. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory

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DATE '99: Proceedings of the conference on Design, automation and test in Europe

January 1999

730 pages

ISBN:1581131216

DOI:10.1145/307418

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 January 1999

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Radi GCalvino ADe Micheli G(2024)In Medio Stat Virtus*: Combining Boolean and Pattern Matching2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473889(404-410)Online publication date: 22-Jan-2024
https://doi.org/10.1109/ASP-DAC58780.2024.10473889
Stok L(2017)EDA3.0: Implications to Logic SynthesisAdvanced Logic Synthesis10.1007/978-3-319-67295-3_1(1-20)Online publication date: 16-Nov-2017
https://doi.org/10.1007/978-3-319-67295-3_1
Marques FRosa LRibas RSapatnekar SReis AZhou HMacii EYan ZMassoud Y(2007)DAG based library-free technology mappingProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228857(293-298)Online publication date: 11-Mar-2007
https://dl.acm.org/doi/10.1145/1228784.1228857
(2007)Congestion Optimization During Technology Mapping and Logic SynthesisRouting Congestion in VLSI Circuits: Estimation and Optimization10.1007/0-387-48550-3_6(189-229)Online publication date: 2007
https://doi.org/10.1007/0-387-48550-3_6
Wei ZChai DNewton AKuehlmann A(2006)Fast Boolean Matching with Don't CaresProceedings of the 7th International Symposium on Quality Electronic Design10.1109/ISQED.2006.65(346-351)Online publication date: 27-Mar-2006
https://dl.acm.org/doi/10.1109/ISQED.2006.65
Chatterjee SMishchenko ABrayton RWang XKam T(2005)Reducing structural bias in technology mappingProceedings of the 2005 IEEE/ACM International conference on Computer-aided design10.5555/1129601.1129675(519-526)Online publication date: 31-May-2005
https://dl.acm.org/doi/10.5555/1129601.1129675
Karandikar SSapatnekar S(2005)Fast comparisons of circuit implementationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2005.86272713:12(1329-1339)Online publication date: 1-Dec-2005
https://dl.acm.org/doi/10.1109/TVLSI.2005.862727
Karandikar SSapatnekar S(2004)Fast Comparisons of Circuit ImplementationsProceedings of the conference on Design, automation and test in Europe - Volume 210.5555/968879.969131Online publication date: 16-Feb-2004
https://dl.acm.org/doi/10.5555/968879.969131
Correia VReis ANatividade da Silva Barros EWagner FCarro LRammig F(2004)Advanced technology mapping for standard-cell generatorsProceedings of the 17th symposium on Integrated circuits and system design10.1145/1016568.1016636(254-259)Online publication date: 4-Sep-2004
https://dl.acm.org/doi/10.1145/1016568.1016636
Karandikar SSapatnekar S(2004)Logical effort based technology mappingProceedings of the 2004 IEEE/ACM International conference on Computer-aided design10.1109/ICCAD.2004.1382611(419-422)Online publication date: 7-Nov-2004
https://dl.acm.org/doi/10.1109/ICCAD.2004.1382611
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