Abstract
Technology mapping transforms a technology independent logic network into gates implemented in a technology library. This chapter focuses on the three phases of technology mapping: decomposition, pattern matching and covering. Traditionally, a lot of work has been focused on tree mapping algorithms, but since most practical circuits are DAGs, DAG mapping algorithms are gaining importance. Different objective functions, namely delay, area, power and reliability motivate the use of different algorithms. Future challenges are outlined.
References
[1]
P. Abouzeid, K. Sakouti, G. Saucier, and F. Poirot, "Multilevel synthesis minimizing the routing factor," in Proc of the 27th ACM/IEEE Design Automation Conference, pp. 365-368, 1990.
[2]
P. Abouzeid, R. Leveugle, G. Saucier, and R. Jamier, "Logic synthesis for automatic layout," in Proc of the Euro ASIC'92, pp. 146-151, 1992.
[3]
F. Beeftink, P. Kudva, D. Kung, and L. Stok, "Gate size selection for standard cell libraries," in Proc of the Int. Conf. on Computer Aided Design, pp. 545-550, Nov 1998.
[4]
Z. Chen and I. Koren, "Technology mapping for hot-carrier reliability enhancement," in Proc of the SPIE - International Society for Optical Engineering, pp. 42-50, 1997.
[5]
G. DeMicheli, Synthesis and Optimization of Digital Systems. New York: McGraw-Hill, 1994.
[6]
E. Detjens, R. Rudell, G. Gannot, A. Wang, and A. Sangiovanni-Vincentelli, "Technology mapping in MIS," in Proc of the Int. Confon ComputerAided Design, pp. 116-119, Nov 1987.
[7]
D. Gregory, K. Bartlett, A. de Geus, and G. Hachtel, "Socrates: a system for automatically synthesizing and optimizing combinational logic," in Proc. 23rd Design Automation Conference, pp. 79-85, 1986.
[8]
J. Grodstein, E. Lehman, H. Harkness, B. Grundmann, and Y. Watanabe, "A delay model for logic synthesis of continuously sized networks," in Proc of the Int. Conf on Computer Aided Design, pp. 458-462, Nov 1995.
[9]
M. A. lyer, L. Stok, and A. Sullivan, "Wavefront technology mapping," in Proc of the Int. Workshop on Logic Synthesis, pp. 419-427, May 1998.
[10]
W. Joyner, L. Trevillyan, D. Brand, T. Nix, and S. Gunderson, "Technology adaptation in logic synthesis," in Proc. 23rd Design Automation Conference, pp. 94-100, June 1986.
[11]
K. Keutzer, "Dagon: Technology binding and local optimization by DAG matching," in Proc of the 24th Design Automation Conference, pp. 341-347, June 1987.
[12]
P. Kudva, "Continuous optimizations in synthesis: The discretization problem," in Proc of Int. Workshop on Logic Synthesis, pp. 408-419, June 1998.
[13]
Y. Kukimoto, R. K. Brayton, and P. Sawkar, "Delay-optimal technology mapping by DAG covering," in Proceedings of the DAC 1998. pp. 348-351, 1998.
[14]
E. Lehman, Y. Watanabe, J. Grodstein, and H. Harkness, "Logic decomposition during technology mapping," in Proc of the Int. Conf on ComputerAided Design, pp. 264-271, Nov 1995.
[15]
E. Lehman, Y. Watanabe, J. Grodstein, and H. Harkness, "Logic decomposition during technology mapping," IEEE Trans on CAD, vol. 16, no. 8, pp. 813-834, August 1997.
[16]
J. Lou, A. Salek, and M. Pedram, "An integrated flow for technology remapping and placement of sub-half-micron circuits," in Proceedings of the ASP-DAC '98, Asia and South Pacific, pp. 295-300, 1998.
[17]
A. Lu, G. Stenz, H. Eisenmann, and F. Johannes, "Technology mapping for simultaneous gate and interconnect optimisation," lEE Proc.-Comput. Digit. Tech., vol. 146, no. I, pp. 21-31, Jan 1999.
[18]
F. Mailhot, "Technology mapping for vlsi circuits exploiting boolean properties and operations," tech. rep., Stanford University, December 1991.
[19]
J. Mohnke, P. Molitor, and S. Malik, "Limits of using signatures for permutation independent boolean comparison," in Proceedings of the ASPDAC. Asia and South Pacific Design Automation Conference, pp. 459-463, 1995.
[20]
M. Pedram and N. Bhat, "Layout driven technology mapping," in Proc of the 28th Design Automation Conference, pp. 99-105, 1991.
[21]
M. Pedram and N. Bhat, "Layout driven logic restructuring/decomposition," in Proc of the Int. Conference on Computer Aided Design, pp. 134-137, 1991.
[22]
R. Rudell, Logic Synthesis for VLSI Design. PhD thesis, University of California, Berkeley, 1989.
[23]
U. Schlichtman and F. Brglez, "Efficient boolean matching in technology mapping with very large cell libraries," in IEEE Custom Integrated Circuits Conference, pp. 3.6.1-3.6.4, 1993.
[24]
K. Shepard et al., "Design methodology for the S/390 parallel enterprise server G4 microprocessors," IBM J. Research and Development, vol. 41, no. 4/5, pp. 515-547, July/September 1997.
[25]
L. Stok et at, "Booledozer logic synthesis for ASICs," IBM J. Research and Development, vol. Vol. 40, no. 4, pp. 407-430, July 1996.
[26]
L. Stok, M. A. lyer, and A. Sullivan, "Wavefront technology mapping," In Proc of Design Automation and Test in Europe, March 1999.
[27]
I. Sutherland and R. Sproull, "The theory of logical effort: Designing for speed on the back of an envelope," in Advanced Research in VLSI, (University of California at Santa Cruz), 1991.
[28]
H. Vaishnav and M. Pedram, "Minimizing the routing cost during logic extraction," in Proc of the 32nd ACM/IEEE Design Automation Conference, pp. 70-75, 1995.
[29]
A. Aho and S. Johnson, "Optimal code generation for expression trees," J. ACM, vol. 23, pp. 488-501, July 1976.
[30]
C. Tsui, M. Pedram, and A. Despain, "Technology decomposition and mapping targeting low power dissipation," in Proceedings of the Design Automation Conference, (Dallas, TX), pp. 68-73, June 1993.
[31]
K. Chaudhary and M. Pedram, "A near-optimal algorithm for technology mapping minimizing area under delay constraints," in Proceedings of the Design Automation Conference, pp. 492-498, June 1992.
[32]
V. Tiwari, Logic and System Design for Low Power Consumption. PhD thesis, Princeton University, Princeton, NJ, 1996.
[33]
V. Tiwari, P. Ashar, and S. Malik, "Technology mapping for low power in logic synthesis," Integration, The VLSI Journal, vol. 20, July 1996.
[34]
H. Touati, Performance Oriented Technology Mapping. PhD thesis, University of California, Berkeley, 1990.
Recommendations
Logic decomposition during technology mapping
ICCAD '95: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided designA problem in technology mapping is that quality of the final implementation depends significantly on the initially provided circuit structure. To resolve this problem, conventional techniques iteratively but separately apply technology independent ...
FPGA technology mapping: a study of optimality
DAC '05: Proceedings of the 42nd annual Design Automation ConferenceThis paper attempts to quantify the optimality of FPGA technology mapping algorithms. We develop an algorithm, based on Boolean satisfiability (SAT), that is able to map a small subcircuit into the smallest possible number of lookup tables (LUTs) needed ...
Testability Considerations in Technology Mapping
ATS '01: Proceedings of the 10th Anniversary Compendium of Papers from Asian Test Symposium 1992-2001We consider the problem of incorporating testability into theprocess of technology mapping. We demonstrate through examplesthat the testability of technology mapped circuits dependson the technology mapping process, and can be controlled duringthis ...
Comments
Information & Contributors
Information
Published In
Publisher
Kluwer Academic Publishers
United States
Publication History
Published: 01 November 2001
Qualifiers
- Chapter
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 0Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0
Reflects downloads up to 06 Oct 2024
Other Metrics
Citations
View Options
View options
Get Access
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in