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DAGON: technology binding and local optimization by DAG matching

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K. KeutzerAuthors Info & Claims

DAC '87: Proceedings of the 24th ACM/IEEE Design Automation Conference

Pages 341 - 347

https://doi.org/10.1145/37888.37940

Published: 01 October 1987 Publication History

Abstract

Technology binding is the process of mapping a technology independent description of a circuit into a particular technology. This paper outlines a formalism of this problem and offers a solution to the problem in terms of matching patterns, describing technology specific cells and optimizations, against a technology independent circuit represented as a directed acyclic graph. This solution is implemented in DAGON. DAGON rests on a firm algorithmic foundation, and is able to guarantee locally optimal matches against a set of over three thousand patterns. DAGON is an integral part of a synthesis system that has been found to provide industrial quality solutions to real circuit design problems.

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Cai YYang ZNi LXie BLi X(2024)Enhancing ASIC Technology Mapping via Parallel Supergate Computing2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617589(289-294)Online publication date: 10-May-2024
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DAGON: technology binding and local optimization by DAG matching

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cover image ACM Conferences

DAC '87: Proceedings of the 24th ACM/IEEE Design Automation Conference

October 1987

840 pages

ISBN:0818607815

DOI:10.1145/37888

Editors:
A. O'Neill,
D. Thomas

Copyright © 1987 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

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Published: 01 October 1987

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DAC87: 24th ACM/IEEE Conference on Design Automation Conference

June 28 - July 1, 1987

Florida, Miami Beach, USA

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DAC '87 Paper Acceptance Rate 138 of 351 submissions, 39%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Cong JHui-Ru Jiang IPosser G(2024)Scheduling and Physical DesignProceedings of the 2024 International Symposium on Physical Design10.1145/3626184.3635290(219-225)Online publication date: 12-Mar-2024
https://dl.acm.org/doi/10.1145/3626184.3635290
Cai YYang ZNi LXie BLi X(2024)Enhancing ASIC Technology Mapping via Parallel Supergate Computing2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617589(289-294)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617589
Radi GCalvino ADe Micheli GKim T(2024)In Medio Stat Virtus*: Combining Boolean and Pattern MatchingProceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473889(404-410)Online publication date: 22-Jan-2024
https://dl.acm.org/doi/10.1109/ASP-DAC58780.2024.10473889
Tu KTang XYu CJosipović LChu ZTu KTang XYu CJosipović LChu Z(2024)Physical ImplementationFPGA EDA10.1007/978-981-99-7755-0_10(165-206)Online publication date: 1-Feb-2024
https://doi.org/10.1007/978-981-99-7755-0_10
Fang CHuang QLiu ZDing RBlanton R(2023)Efficient Test Chip Design via Smart ComputationACM Transactions on Design Automation of Electronic Systems10.1145/355839328:2(1-31)Online publication date: 22-Mar-2023
https://dl.acm.org/doi/10.1145/3558393
Rashed MThijssen SJha SYao FEwetz R(2023)STREAM: Toward READ-Based In-Memory Computing for Streaming-Based Processing for Data-Intensive ApplicationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.326372342:11(3854-3867)Online publication date: Nov-2023
https://doi.org/10.1109/TCAD.2023.3263723
Liu JNi LLi XZhou MChen LLi XZhao QMa S(2023)AiMap: Learning to Improve Technology Mapping for ASICs via Delay Prediction2023 IEEE 41st International Conference on Computer Design (ICCD)10.1109/ICCD58817.2023.00059(344-347)Online publication date: 6-Nov-2023
https://doi.org/10.1109/ICCD58817.2023.00059
Grosnit AZimmer MTutunov RLi XChen LYang FYuan MBou-Ammar H(2023)Lightweight Structural Choices Operator for Technology Mapping2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247838(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247838
Rashed MJha SYao FEwetz RBolchini CO'Connor IVerbauwhede IWille R(2022)Hybrid digital-digital in-memory computingProceedings of the 2022 Conference & Exhibition on Design, Automation & Test in Europe10.5555/3539845.3540124(1177-1180)Online publication date: 14-Mar-2022
https://dl.acm.org/doi/10.5555/3539845.3540124
Rashed MJha SEwetz RMitra TYoung EXiong J(2022)Logic Synthesis for Digital In-Memory ComputingProceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design10.1145/3508352.3549348(1-9)Online publication date: 30-Oct-2022
https://dl.acm.org/doi/10.1145/3508352.3549348
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