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- research-articleFebruary 2009
Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arraysFebruary 2009, Pages 43–52https://doi.org/10.1145/1508128.1508136FPGA user clocks are slow enough that only a fraction of the interconnect's bandwidth is actually used. There may be an opportunity to use throughput-oriented interconnect to decrease routing congestion and wire area using on-chip serial signaling, ...
- research-articleJune 2007
MOUSETRAP: high-speed transition-signaling asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 15, Issue 6June 2007, Pages 684–698https://doi.org/10.1109/TVLSI.2007.898732An asynchronous pipeline style is introduced for high-speed applications, called MOUSETRAP. The pipeline uses standard transparent latches and static logic in its datapath, and small latch controllers consisting of only a single gate per pipeline stage. ...
- research-articleAugust 2005
Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 13, Issue 8August 2005, Pages 899–910https://doi.org/10.1109/TVLSI.2005.853611In modern-day VLSI systems, performance and manufacturing costs are being driven by the on-chip wiring needs due to the continuous increase in the number of transistors. This paper proposes a low overhead wave-pipelined multiplexed (WPM) routing ...
- ArticleMarch 2005
Energy Efficient Surfing
ASYNC '05: Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and SystemsMarch 2005, Pages 2–11https://doi.org/10.1109/ASYNC.2005.20Surfing is a latchless pipelining technique where the propagation delays of gates and other logic functions are modulated to produce event attractors. We describe a test chip that demonstrates a surfing pipeline ring and then introduce new circuits that ...
- research-articleMarch 2005
Optimization of throughput performance for low-power VLSI interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 13, Issue 3March 2005, Pages 308–318https://doi.org/10.1109/TVLSI.2004.842898The technique of optimal voltage scaling and repeater insertion is analyzed in this paper to reduce power dissipation on global interconnects. An analytical model for the maximum bitrate of a very large scale integration interconnect with repeaters has ...
- ArticleOctober 2002
Wave pipelining for application-specific networks-on-chips
CASES '02: Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systemsOctober 2002, Pages 198–201https://doi.org/10.1145/581630.581661This paper presents methods for optimizing application-specific networks-on-chips (NoCs). We show that wave pipelining provides more energy efficient data transport than non-wave pipelined communication. We observe 52% energy saving, 60% transistor area ...
- research-articleDecember 1999
Statistical analysis of timing rules for high-speed synchronous VLSI systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 7, Issue 4Dec. 1999, Pages 477–482https://doi.org/10.1109/92.805754Timing skew has been the major limitation for high-speed synchronous operation of a VLSI system. In this paper, a statistical timing model that accounts for both static and random timing skew is proposed. Based on this model, we analyze the timing rules ...
- ArticleJanuary 1996
Dual rail static CMOS architecture for wave pipelining
VLSID '96: Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile CommunicationJanuary 1996, Page 335Wave-pipelining is a special pipelining technique used in digital systems to achieve high throughput, with the use of gate capacitance as storage elements. An ideal system should have minimal delay variations amongst all paths. A dual-rail static CMOS (...
- ArticleOctober 1995
Concurrent timing optimization of latch-based digital systems
ICCD '95: Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and ProcessorsOctober 1995, Page 680Many techniques have been proposed to optimize digital system timing. Each technique can be advantageous in particular applications, however they are most often applied individually rather than concurrently. The framework presented here allows for ...
- ArticleJuly 1995
The SNAP Project: Towards Sub-Nanosecond Arithmetic
ARITH '95: Proceedings of the 12th Symposium on Computer ArithmeticJuly 1995, Page 75SNAP - the Stanford subnanosecond arithmetic processor - is an interdisciplinary effort to develop theory, tools, and technology for realizing an arithmetic processor with execution rates under 1 ns. Specific improvements in clocking methods, floating-...