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Article

Dual rail static CMOS architecture for wave pipelining

Published: 03 January 1996 Publication History

Abstract

Wave-pipelining is a special pipelining technique used in digital systems to achieve high throughput, with the use of gate capacitance as storage elements. An ideal system should have minimal delay variations amongst all paths. A dual-rail static CMOS (DRSCMOS) technique is presented for wave-pipelining. The availability of multi-functional basic building blocks and their low power consumption makes this an attractive approach.

References

[1]
D. Wong, G. DeMicheli, and M. Flynn, "Designing high-performance digital circuits using wave-pipelining: Algorithms and practical experiences," IEEE Trans. CAD of Integrated Circuits and Systems, vol. 12, pp. 25-46, 1993.
[2]
C. Gray, W. Liu, and R. Cavin, "Timing Constrants for Wave-Pipelining System," IEEE Trans. CAD of Integrated Circuits and Systems, vol. 13, pp. 987- 1004, 1994.
[3]
C. Gray, T. Hughes, S. Arora, W. Liu, and R. Cavin, "Theoretical and practical issues in CMOS wave-pipelining," in Proc. VLSI'91 , (Edinburgh, UK), pp. 397-409, 1991.
[4]
F. Klass and J. Mulder, "Use of CMOS technology in wave-pipelining," in Proc. Fifth Intl. Conf. VLSI Design, (Bangalore, India), pp. 303-308, 1992.
[5]
D. Ghosh and S. Nandy, "A 400 MHz wave-pipelined 8x8-bit multiplier in CMOS technology," in Proc. Intl. Conf. VLSI DESIGN'93, (Bangalore, India), pp. 198-201, 1993.
[6]
X. Zhang and R. Sridhar, "CMOS wave-pipelining using transmission gate logic," in Proc. IEEE Intl. ASIC Conf. and Exhibit, (Rochester, NY), pp. 92- 95, 1994.
[7]
F. Klass, M. Flynn, and A. V. D. Goor, "Fast multiplication in VLSI using wave-pipelining techniques," IEEE Trans. on VLSI Signal Processing, 1995.
[8]
W. Liu, C. Gray, D. Fan, W. Farlow, T. Hughes, and R. Cavin, "A 250-MHz Wave-Pipelined adder in 2um CMOS," IEEE J. Solid-state Circuits, vol. 29, pp. 1117-1128, 1994.

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Published In

cover image Guide Proceedings
VLSID '96: Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
January 1996
ISBN:0818672285

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IEEE Computer Society

United States

Publication History

Published: 03 January 1996

Author Tags

  1. CMOS logic circuits
  2. DRSCMOS
  3. capacitance
  4. combinational circuits
  5. combinational logic block
  6. delay variations
  7. delays
  8. digital systems
  9. dual rail static CMOS architecture
  10. gate capacitance
  11. multi-functional basic building blocks
  12. pipeline processing
  13. power consumption
  14. storage elements
  15. throughput
  16. timing
  17. wave pipelining

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